chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/memory/dcbz.md
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migration/project-root/ppc-manual/memory/dcbz.md
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# `dcbz` — Data Cache Block Clear to Zero
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> **Category:** [Memory](../categories/memory.md) · **Form:** [DCBZ](../forms/DCBZ.md) · **Opcode:** `0x7c0007ec`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `dcbz` | `dcbz` | — | Data Cache Block Clear to Zero |
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| `dcbz128` | `dcbz128` | — | Data Cache Block Clear to Zero 128 |
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## Syntax
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```asm
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dcbz [RA0], [RB]
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dcbz128 [RA0], [RB]
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```
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## Encoding
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### `dcbz` — form `DCBZ`
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- **Opcode word:** `0x7c0007ec`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `1014`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (31) |
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| 6–10 | `—` | reserved |
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| 11–15 | `RA` | base register (0 ⇒ literal 0) |
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| 16–20 | `RB` | offset register |
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| 21–30 | `XO` | extended opcode (1014 for dcbz / 1010 for dcbz128) |
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| 31 | `—` | reserved |
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### `dcbz128` — form `DCBZ`
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- **Opcode word:** `0x7c2007ec`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `1014`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (31) |
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| 6–10 | `—` | reserved |
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| 11–15 | `RA` | base register (0 ⇒ literal 0) |
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| 16–20 | `RB` | offset register |
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| 21–30 | `XO` | extended opcode (1014 for dcbz / 1010 for dcbz128) |
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| 31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | dcbz: read; dcbz128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | dcbz: read; dcbz128: read | Source GPR. |
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## Register Effects
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### `dcbz`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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### `dcbz128`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`dcbz`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="dcbz"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1159`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1159)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:19`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L19)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:886`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L886)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1694-1705`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1694-L1705)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::dcbz => {
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// Zero 32 bytes at effective address
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) as u32) & !31;
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() { t.invalidate_for_write(ea); }
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}
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for i in 0..8 {
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mem.write_u32(ea + i * 4, 0);
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}
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ctx.pc += 4;
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}
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```
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</details>
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**`dcbz128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="dcbz128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1171`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1171)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:19`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L19)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:887`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L887)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1706-1717`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1706-L1717)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::dcbz128 => {
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// Zero 128 bytes
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) as u32) & !127;
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() { t.invalidate_for_write(ea); }
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}
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for i in 0..32 {
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mem.write_u32(ea + i * 4, 0);
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}
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Cache-line size mismatch.** Stock PowerPC `dcbz` zeroes one architectural cache line — 32 bytes on classic POWER, but the **Xenon's L1 line is 128 bytes**. Microsoft added `dcbz128` (encoded with bit-9 set so `RT` field reads as `1`) to clear a true Xenon line in one instruction. Most Xbox 360 code therefore emits `dcbz128`; a stray `dcbz` only zeroes 32 bytes and silently leaves the rest of the line uncleared.
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- **Alignment is forced via mask.** The effective address is masked by `~31` (`dcbz`) or `~127` (`dcbz128`) before writing — the low bits are dropped, not validated. Calling `dcbz r0, r3` with `r3 = 0x10037` writes zeros to `0x10000..0x1007F`, not `0x10037..0x100B6`.
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- **No memory read; pure write.** Real hardware allocates the line in cache and may skip a read-from-memory fill ("cache-line zero" optimisation). Xenia simulates the architectural effect — 32 (or 128) bytes of zero in target memory — without modelling cache state.
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- **`RA0` semantics.** `RA = 0` selects literal zero as the base, so `dcbz128 0, RB` zeros the line containing address `RB`. The update form does not exist for cache-control instructions.
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- **Block-fill idiom.** Compilers and hand-written copy loops pair `dcbz128` with `stvx` / `stw` sequences to avoid the cache-line read-allocate that a cold store would trigger. Skipping the read is the entire point.
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- **Privilege.** `dcbz` is unprivileged (problem-state); does not require supervisor mode. It can fault on protection or unmapped memory like an ordinary store.
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- **Sequencing.** Not synchronising. Pair with [`sync`](sync.md) / [`lwsync`](sync.md) when the zeros must be visible before subsequent loads on another thread.
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## Related Instructions
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- [`dcbf`](dcbf.md) — flush a line back to memory.
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- [`dcbst`](dcbst.md) — store-through (write-back without invalidate).
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- [`dcbi`](dcbi.md) — invalidate (privileged on most cores).
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- [`dcbt`](dcbt.md), [`dcbtst`](dcbtst.md) — touch / touch-for-store hints.
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- [`icbi`](icbi.md) — instruction-cache invalidate (companion to data-cache control).
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- [`stvx`](stvx.md), [`stw`](stw.md) — typical pair-mates in block-fill loops.
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## IBM Reference
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- [AIX 7.3 — `dcbz` (Data Cache Block Set to Zero)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-dcbz-data-cache-block-set-zero-instruction)
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- Microsoft Xbox 360 XDK / `Xenon Programming Guide` — for `dcbz128` specifics; `PowerISA v2.07B Book II` § "Storage Control Instructions" for the architectural baseline.
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