chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on another machine can be brought up to identical configuration via migration/setup.sh: - claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/ (103 files, 1.1 MB - MEMORY.md + every project_xenia_rs_*.md from audits addis_signext through audit-058) - project-root/dot-claude/ <project-root>/.claude/settings.json (Stop hook + permissions) - project-root/ppc-manual/ <project-root>/ppc-manual/ (PowerPC reference docs, 397 files, 3.7 MB) - project-root/run-canary.sh <project-root>/run-canary.sh - README.md Human-readable setup checklist - setup.sh Idempotent installer (also reclones xenia-canary at pinned HEAD 6de80dffe) - MANIFEST.md Per-file mapping + per-file-not-bundled restoration recipe Excluded from bundle (not shippable via git): - Sylpheed ISO (7.8 GB; copyright; manual copy required) - sylpheed.db (395 MB; regenerable from XEX via analysis tooling) - target/ build artifacts (rebuild on target) - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed) - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed) - xenia-canary checkout (setup.sh reclones from git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
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--- a/migration/project-root/ppc-manual/memory/lbz.md
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+# `lbz` — Load Byte and Zero
+
+> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x88000000`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `lbz` | `lbz` | — | Load Byte and Zero |
+| `lbzu` | `lbzu` | — | Load Byte and Zero with Update |
+| `lbzux` | `lbzux` | — | Load Byte and Zero with Update Indexed |
+| `lbzx` | `lbzx` | — | Load Byte and Zero Indexed |
+
+## Syntax
+
+```asm
+lbz [RD], [d]([RA0])
+lbzu [RD], [d]([RA])
+lbzux [RD], [RA], [RB]
+lbzx [RD], [RA0], [RB]
+```
+
+## Encoding
+
+### `lbz` — form `D`
+
+- **Opcode word:** `0x88000000`
+- **Primary opcode (bits 0–5):** `34`
+- **Extended opcode:** —
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT` | destination GPR (or RS when storing) |
+| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
+| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
+
+### `lbzu` — form `D`
+
+- **Opcode word:** `0x8c000000`
+- **Primary opcode (bits 0–5):** `35`
+- **Extended opcode:** —
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT` | destination GPR (or RS when storing) |
+| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
+| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
+
+### `lbzux` — form `X`
+
+- **Opcode word:** `0x7c0000ee`
+- **Primary opcode (bits 0–5):** `31`
+- **Extended opcode:** `119`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT/FRT/VRT` | destination |
+| 11–15 | `RA/FRA/VRA` | source A |
+| 16–20 | `RB/FRB/VRB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `Rc` | record-form flag |
+
+### `lbzx` — form `X`
+
+- **Opcode word:** `0x7c0000ae`
+- **Primary opcode (bits 0–5):** `31`
+- **Extended opcode:** `87`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT/FRT/VRT` | destination |
+| 11–15 | `RA/FRA/VRA` | source A |
+| 16–20 | `RB/FRB/VRB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `Rc` | record-form flag |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+| `RA0` | lbz: read; lbzx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
+| `d` | lbz: read; lbzu: read | 16-bit signed displacement (`d`) added to the base address register. |
+| `RD` | lbz: write; lbzu: write; lbzux: write; lbzx: write | Destination GPR. |
+| `RA` | lbzu: read; lbzu: write; lbzux: read; lbzux: write | Source GPR (`r0`–`r31`). |
+| `RB` | lbzux: read; lbzx: read | Source GPR. |
+
+## Register Effects
+
+### `lbz`
+
+- **Reads (always):** `RA0`, `d`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`
+- **Writes (conditional):** _none_
+
+### `lbzu`
+
+- **Reads (always):** `RA`, `d`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`, `RA`
+- **Writes (conditional):** _none_
+
+### `lbzux`
+
+- **Reads (always):** `RA`, `RB`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`, `RA`
+- **Writes (conditional):** _none_
+
+### `lbzx`
+
+- **Reads (always):** `RA0`, `RB`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`
+- **Writes (conditional):** _none_
+
+## Status-Register Effects
+
+_No condition-register or status-register effects._
+
+## Operation (pseudocode)
+
+```
+EA <- (RA|0) + EXTS(d)
+RT <- 0x00000000_000000_00 || MEM(EA, 1)
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`lbz`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lbz"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:72`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L72)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:34`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L34)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:357`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L357)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1024-1029`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1024-L1029)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::lbz => {
+            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
+            let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u8(ea) as u64;
+            ctx.pc += 4;
+        }
+```
+</details>
+
+**`lbzu`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lbzu"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:92`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L92)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:34`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L34)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:358`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L358)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1030-1035`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1030-L1035)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::lbzu => {
+            let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u8(ea) as u64;
+            ctx.gpr[instr.ra()] = ea as u64;
+            ctx.pc += 4;
+        }
+```
+</details>
+
+**`lbzux`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lbzux"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:104`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L104)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:34`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L34)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:776`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L776)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1042-1047`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1042-L1047)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::lbzux => {
+            let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u8(ea) as u64;
+            ctx.gpr[instr.ra()] = ea as u64;
+            ctx.pc += 4;
+        }
+```
+</details>
+
+**`lbzx`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lbzx"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:115`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L115)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:34`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L34)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:774`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L774)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1036-1041`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1036-L1041)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::lbzx => {
+            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
+            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u8(ea) as u64;
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **Single-byte read.** The smallest scalar load. No endian concerns at the byte level — `MEM(EA, 1)` returns the literal byte at address `EA`, regardless of host or target byte order.
+- **Zero-extension to 64 bits.** The high 56 bits of `RT` become zero. Use [`lha`](lha.md) / [`lhax`](lha.md) family for sign-extending byte-equivalent semantics; there is no PowerPC "load byte sign-extended" — you must `lbz` then `extsb` (or use `lha` on a half).
+- **`RA0` (non-update forms).** When `RA = 0` in `lbz` / `lbzx`, the base is the literal zero, so `lbz RT, 0x4000(0)` reads from absolute address `0x4000`. Update forms `lbzu` / `lbzux` invoke `RA = 0` (and `RA = RT`) as invalid forms; xenia's interpreter does not check, so well-formed compiler output is assumed.
+- **Update-form post-write.** `lbzu` / `lbzux` write the computed `EA` back to `RA` after the load; the snapshot first reads, then assigns `RA ← EA`, matching IBM's "the load and update happen as one operation" wording.
+- **No alignment requirement.** A byte load is intrinsically aligned. Xenon does not raise alignment exceptions for any byte access.
+- **Common in string and table-lookup code.** Most uses are character-string scans, jump-table dispatches, and packed-bool reads. Compilers also use `lbz` to materialise small immediate constants stored in `.rodata`.
+
+## Related Instructions
+
+- [`lhz`](lhz.md), [`lwz`](lwz.md), [`ld`](ld.md) — wider zero-extending loads in the same family.
+- [`lha`](lha.md), [`lwa`](lwa.md) — sign-extending siblings (no `lba` exists; use `lbz` + `extsb`).
+- [`stb`](stb.md), [`stbu`](stb.md), [`stbx`](stb.md), [`stbux`](stb.md) — the corresponding stores.
+- [`lwbrx`](lwbrx.md), [`lhbrx`](lhbrx.md) — byte-reversed multi-byte loads (no byte-equivalent needed).
+- [`lmw`](lmw.md), [`lswi`](lswi.md), [`lswx`](lswx.md) — multi-word / string loads for bulk transfer.
+
+## IBM Reference
+
+- [AIX 7.3 — `lbz` (Load Byte and Zero)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lbz-load-byte-zero-instruction)
+- [AIX 7.3 — `lbzu` (Load Byte and Zero with Update)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lbzu-load-byte-zero-update-instruction)