chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on another machine can be brought up to identical configuration via migration/setup.sh: - claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/ (103 files, 1.1 MB - MEMORY.md + every project_xenia_rs_*.md from audits addis_signext through audit-058) - project-root/dot-claude/ <project-root>/.claude/settings.json (Stop hook + permissions) - project-root/ppc-manual/ <project-root>/ppc-manual/ (PowerPC reference docs, 397 files, 3.7 MB) - project-root/run-canary.sh <project-root>/run-canary.sh - README.md Human-readable setup checklist - setup.sh Idempotent installer (also reclones xenia-canary at pinned HEAD 6de80dffe) - MANIFEST.md Per-file mapping + per-file-not-bundled restoration recipe Excluded from bundle (not shippable via git): - Sylpheed ISO (7.8 GB; copyright; manual copy required) - sylpheed.db (395 MB; regenerable from XEX via analysis tooling) - target/ build artifacts (rebuild on target) - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed) - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed) - xenia-canary checkout (setup.sh reclones from git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
commit e6d43a23ac
505 changed files with 86028 additions and 0 deletions
--- a/migration/project-root/ppc-manual/memory/ld.md
+++ b/migration/project-root/ppc-manual/memory/ld.md
@@ -0,0 +1,251 @@
+# `ld` — Load Doubleword
+
+> **Category:** [Memory](../categories/memory.md) · **Form:** [DS](../forms/DS.md) · **Opcode:** `0xe8000000`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `ld` | `ld` | — | Load Doubleword |
+| `ldu` | `ldu` | — | Load Doubleword with Update |
+| `ldux` | `ldux` | — | Load Doubleword with Update Indexed |
+| `ldx` | `ldx` | — | Load Doubleword Indexed |
+
+## Syntax
+
+```asm
+ld [RD], [ds]([RA0])
+ldu [RD], [ds]([RA])
+ldux [RD], [RA], [RB]
+ldx [RD], [RA0], [RB]
+```
+
+## Encoding
+
+### `ld` — form `DS`
+
+- **Opcode word:** `0xe8000000`
+- **Primary opcode (bits 0–5):** `58`
+- **Extended opcode:** —
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT` | destination GPR (or RS) |
+| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
+| 16–29 | `DS` | 14-bit signed word-scaled displacement |
+| 30–31 | `XO` | extended opcode |
+
+### `ldu` — form `DS`
+
+- **Opcode word:** `0xe8000001`
+- **Primary opcode (bits 0–5):** `58`
+- **Extended opcode:** —
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT` | destination GPR (or RS) |
+| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
+| 16–29 | `DS` | 14-bit signed word-scaled displacement |
+| 30–31 | `XO` | extended opcode |
+
+### `ldux` — form `X`
+
+- **Opcode word:** `0x7c00006a`
+- **Primary opcode (bits 0–5):** `31`
+- **Extended opcode:** `53`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT/FRT/VRT` | destination |
+| 11–15 | `RA/FRA/VRA` | source A |
+| 16–20 | `RB/FRB/VRB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `Rc` | record-form flag |
+
+### `ldx` — form `X`
+
+- **Opcode word:** `0x7c00002a`
+- **Primary opcode (bits 0–5):** `31`
+- **Extended opcode:** `21`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT/FRT/VRT` | destination |
+| 11–15 | `RA/FRA/VRA` | source A |
+| 16–20 | `RB/FRB/VRB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `Rc` | record-form flag |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+| `RA0` | ld: read; ldx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
+| `ds` | ld: read; ldu: read | 14-bit signed word-aligned displacement (`DS << 2`). |
+| `RD` | ld: write; ldu: write; ldux: write; ldx: write | Destination GPR. |
+| `RA` | ldu: read; ldu: write; ldux: read; ldux: write | Source GPR (`r0`–`r31`). |
+| `RB` | ldux: read; ldx: read | Source GPR. |
+
+## Register Effects
+
+### `ld`
+
+- **Reads (always):** `RA0`, `ds`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`
+- **Writes (conditional):** _none_
+
+### `ldu`
+
+- **Reads (always):** `RA`, `ds`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`, `RA`
+- **Writes (conditional):** _none_
+
+### `ldux`
+
+- **Reads (always):** `RA`, `RB`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`, `RA`
+- **Writes (conditional):** _none_
+
+### `ldx`
+
+- **Reads (always):** `RA0`, `RB`
+- **Reads (conditional):** _none_
+- **Writes (always):** `RD`
+- **Writes (conditional):** _none_
+
+## Status-Register Effects
+
+_No condition-register or status-register effects._
+
+## Operation (pseudocode)
+
+```
+EA <- (RA|0) + EXTS(ds || 0b00)
+RT <- MEM(EA, 8)
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`ld`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="ld"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:347`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L347)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:36`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L36)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:380`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L380)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1096-1101`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1096-L1101)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::ld => {
+            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
+            let ea = ea.wrapping_add(instr.ds() as i64 as u64) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u64(ea);
+            ctx.pc += 4;
+        }
+```
+</details>
+
+**`ldu`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="ldu"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:367`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L367)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:36`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L36)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:381`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L381)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1126-1131`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1126-L1131)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::ldu => {
+            let ea = ctx.gpr[instr.ra()].wrapping_add(instr.ds() as i64 as u64) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u64(ea);
+            ctx.gpr[instr.ra()] = ea as u64;
+            ctx.pc += 4;
+        }
+```
+</details>
+
+**`ldux`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="ldux"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:378`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L378)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:36`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L36)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:764`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L764)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1132-1137`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1132-L1137)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::ldux => {
+            let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u64(ea);
+            ctx.gpr[instr.ra()] = ea as u64;
+            ctx.pc += 4;
+        }
+```
+</details>
+
+**`ldx`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="ldx"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:389`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L389)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:36`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L36)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:755`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L755)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1102-1107`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1102-L1107)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::ldx => {
+            let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
+            let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
+            ctx.gpr[instr.rd()] = mem.read_u64(ea);
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **DS-form, not D-form.** The displacement is 14 bits scaled by 4 (`EXTS(ds || 0b00)`), giving a signed range of ±32 KiB in 4-byte steps. Bits 30–31 are the extended opcode used to distinguish `ld` (XO=0) from `ldu` (XO=1). The assembler accepts a normal byte displacement and verifies divisibility by 4.
+- **Big-endian read.** The 64 bits at `EA..EA+7` form the loaded value, most-significant byte first. Xenia-rs's `mem.read_u64` returns the host-native value of that big-endian doubleword.
+- **No zero/sign-extension question.** `ld` already fills the entire 64-bit register; there is no `lda` (load doubleword algebraic) — the doubleword is the architectural maximum.
+- **`RA0` (non-update forms).** `RA = 0` in `ld` and `ldx` means base is literal zero. `ld RT, 0x100(0)` reads from absolute `0x100`.
+- **Update-form invalid forms.** `ldu` / `ldux` invoke "RA = 0" and "RA = RT" as invalid forms. AIX docs say results are undefined; xenia performs the read first, then writes back `RA ← EA`, which would silently destroy the loaded value if `RA == RT`.
+- **Alignment.** Xenon does not enforce doubleword alignment for `ld` itself — unaligned 8-byte loads are tolerated. However, real POWER cores may take an alignment exception on some implementations; portable code keeps doublewords 8-byte aligned.
+- **64-bit pointer / counter loads.** Although Xbox 360 user code is 32-bit, kernel structures and TOC entries are doublewords; `ld` is the standard load for them.
+
+## Related Instructions
+
+- [`lwz`](lwz.md), [`lhz`](lhz.md), [`lbz`](lbz.md) — narrower zero-extending loads.
+- [`lwa`](lwa.md), [`lha`](lha.md) — sign-extending loads (no `lda` exists; `ld` already fills the register).
+- [`ldbrx`](ldbrx.md) — byte-reversed doubleword load.
+- [`ldarx`](ldarx.md) / [`stdcx`](stdcx.md) — load-reserve / store-conditional doubleword pair.
+- [`std`](std.md), [`stdu`](std.md), [`stdx`](std.md), [`stdux`](std.md) — corresponding stores.
+
+## IBM Reference
+
+- [AIX 7.3 — `ld` (Load Doubleword)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-ld-load-doubleword-instruction)
+- [AIX 7.3 — `ldu` / `ldux` / `ldx`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-ldu-load-doubleword-update-instruction)