chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
248
migration/project-root/ppc-manual/memory/lfd.md
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248
migration/project-root/ppc-manual/memory/lfd.md
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# `lfd` — Load Floating-Point Double
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> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xc8000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `lfd` | `lfd` | — | Load Floating-Point Double |
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| `lfdu` | `lfdu` | — | Load Floating-Point Double with Update |
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| `lfdux` | `lfdux` | — | Load Floating-Point Double with Update Indexed |
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| `lfdx` | `lfdx` | — | Load Floating-Point Double Indexed |
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## Syntax
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```asm
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lfd [FD], [d]([RA0])
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lfdu [FD], [d]([RA])
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lfdux [FD], [RA], [RB]
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lfdx [FD], [RA0], [RB]
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```
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## Encoding
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### `lfd` — form `D`
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- **Opcode word:** `0xc8000000`
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- **Primary opcode (bits 0–5):** `50`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `lfdu` — form `D`
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- **Opcode word:** `0xcc000000`
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- **Primary opcode (bits 0–5):** `51`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `lfdux` — form `X`
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- **Opcode word:** `0x7c0004ee`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `631`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `lfdx` — form `X`
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- **Opcode word:** `0x7c0004ae`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `599`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | lfd: read; lfdx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `d` | lfd: read; lfdu: read | 16-bit signed displacement (`d`) added to the base address register. |
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| `FD` | lfd: write; lfdu: write; lfdux: write; lfdx: write | Destination floating-point register. |
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| `RA` | lfdu: read; lfdu: write; lfdux: read; lfdux: write | Source GPR (`r0`–`r31`). |
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| `RB` | lfdux: read; lfdx: read | Source GPR. |
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## Register Effects
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### `lfd`
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- **Reads (always):** `RA0`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`
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- **Writes (conditional):** _none_
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### `lfdu`
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- **Reads (always):** `RA`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`, `RA`
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- **Writes (conditional):** _none_
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### `lfdux`
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- **Reads (always):** `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`, `RA`
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- **Writes (conditional):** _none_
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### `lfdx`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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EA <- (RA|0) + EXTS(d)
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FRT <- MEM(EA, 8)
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`lfd`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfd"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:912`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L912)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:38`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L38)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:373`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L373)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1152-1157`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1152-L1157)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lfd => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
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ctx.fpr[instr.rd()] = mem.read_f64(ea);
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ctx.pc += 4;
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}
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```
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</details>
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**`lfdu`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfdu"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:925`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L925)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:38`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L38)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:374`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L374)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1176-1181`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1176-L1181)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lfdu => {
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let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
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ctx.fpr[instr.rd()] = mem.read_f64(ea);
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ctx.gpr[instr.ra()] = ea as u64;
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ctx.pc += 4;
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}
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```
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</details>
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**`lfdux`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfdux"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:936`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L936)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:38`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L38)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:827`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L827)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1182-1187`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1182-L1187)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lfdux => {
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let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
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ctx.fpr[instr.rd()] = mem.read_f64(ea);
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ctx.gpr[instr.ra()] = ea as u64;
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ctx.pc += 4;
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}
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```
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</details>
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**`lfdx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfdx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:947`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L947)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:38`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L38)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:826`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L826)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1158-1163`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1158-L1163)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lfdx => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
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ctx.fpr[instr.rd()] = mem.read_f64(ea);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Bit-exact double load.** Reads 8 bytes and places them directly into `FRT` as IEEE-754 binary64. No format conversion is performed (contrast `lfs`, which expands single→double).
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- **No FPSCR side effects.** `lfd` cannot raise IEEE exceptions: it neither rounds nor inspects the value. A signalling NaN read this way stays a signalling NaN until it is consumed by an arithmetic op.
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- **`RA0` semantics.** In the non-update forms (`lfd`, `lfdx`), `RA = 0` selects literal zero — `lfd FT, 0(0)` loads from absolute address 0. Update forms `lfdu` / `lfdux` invoke `RA = 0` and `RA = RT` (here `RA` is GPR; `RT` is FPR, so the latter cannot collide) as invalid forms when `RA = 0`.
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- **Alignment.** Xenon tolerates unaligned 8-byte FP loads; PowerISA technically permits implementations to raise alignment exceptions for FP loads, so portable code uses 8-byte aligned addresses.
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- **Big-endian read.** Bytes are interpreted big-endian: byte at `EA` is bits 0–7 of the IEEE pattern (sign + part of exponent), byte at `EA+7` is bits 56–63 of the mantissa. `mem.read_f64` in xenia handles the host-side byte-swap.
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- **MSR[FP] required.** Like all FP-register accesses, `lfd` requires the FP unit be enabled (MSR[FP]=1). Otherwise a Floating-Point Unavailable interrupt is raised. Xenia assumes FP is always enabled in user code.
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- **Pair with [`stfd`](stfd.md).** Store-double is the symmetric counterpart.
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## Related Instructions
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- [`lfs`](lfs.md) — single-precision load with format conversion to double.
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- [`stfd`](stfd.md), [`stfdu`](stfd.md), [`stfdx`](stfd.md), [`stfdux`](stfd.md) — corresponding stores.
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- [`stfiwx`](stfiwx.md) — store-FP-as-integer-word (the asymmetric oddity in the FP load/store family).
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- [`ld`](ld.md) — integer doubleword load (same width, GPR target).
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## IBM Reference
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- [AIX 7.3 — `lfd` (Load Floating-Point Double)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lfd-load-floating-point-double-instruction)
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- [AIX 7.3 — `lfdu` / `lfdx` / `lfdux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lfdu-load-floating-point-double-update-instruction)
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Reference in New Issue
Block a user