chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

migration/project-root/ppc-manual/memory/lvebx.md

@@ -0,0 +1,135 @@
+# `lvebx` — Load Vector Element Byte Indexed
+
+> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00000e`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `lvebx` | `lvebx` | — | Load Vector Element Byte Indexed |
+
+## Syntax
+
+```asm
+lvebx [VD], [RA0], [RB]
+```
+
+## Encoding
+
+### `lvebx` — form `X`
+
+- **Opcode word:** `0x7c00000e`
+- **Primary opcode (bits 0–5):** `31`
+- **Extended opcode:** `7`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT/FRT/VRT` | destination |
+| 11–15 | `RA/FRA/VRA` | source A |
+| 16–20 | `RB/FRB/VRB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `Rc` | record-form flag |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+| `RA0` | lvebx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
+| `RB` | lvebx: read | Source GPR. |
+| `VD` | lvebx: write | Destination vector register. |
+
+## Register Effects
+
+### `lvebx`
+
+- **Reads (always):** `RA0`, `RB`
+- **Reads (conditional):** _none_
+- **Writes (always):** `VD`
+- **Writes (conditional):** _none_
+
+## Status-Register Effects
+
+_No condition-register or status-register effects._
+
+## Operation (pseudocode)
+
+```
+; Pseudocode derives directly from the xenia-rs interpreter
+; arm (see Implementation References). Operation semantics:
+;   - Read source operands from the fields listed under Operands.
+;   - Apply the arithmetic / logical / memory action described
+;     in the Description field above.
+;   - Write results to the destination register(s); update any
+;     status bits enumerated under Status-Register Effects.
+; Consult the IBM AIX reference link under IBM Reference for
+; canonical PPC-style pseudocode where xenia's expression is
+; terse.
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`lvebx`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvebx"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:73`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L73)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:44`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L44)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:752`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L752)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1872-1883`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1872-L1883)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::lvebx => {
+            // Load 1 byte from EA into vD[EA & 0xF]. PowerISA marks the
+            // other lanes as "undefined" but real Xenon (and Canary)
+            // preserve their prior contents, so seed from vD.
+            let base = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
+            let ea = base.wrapping_add(ctx.gpr[instr.rb()]) as u32;
+            let slot = (ea & 0xF) as usize;
+            let mut bytes = ctx.vr[instr.rd()].as_bytes();
+            bytes[slot] = mem.read_u8(ea);
+            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(bytes);
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **Single-byte element load.** Architecturally `lvebx` loads exactly **one** byte from `EA` and places it in lane `EA mod 16` of the destination vector; the other 15 lanes are *undefined* (PowerISA permits implementations to leave them as garbage). Real hardware: lane `EA mod 16` gets the byte, others are unspecified.
+- **Xenia simplification — full-line read.** The xenia snapshot is shared with `lvehx` / `lvewx` and reads the **entire 16-byte aligned line** (`ea & ~0xF`, then 16 bytes), placing it in `VD`. This is stronger than the architectural guarantee — every lane is filled with whatever happened to be at the line — but matches the practical idiom of using these single-element loads to assemble a vector. Code that depends on undefined-lane behaviour will still produce well-defined output under xenia.
+- **Operand order subtle.** Unlike `lvx`, the architectural EA is **not** masked. The lane is `EA & 0xF`. Xenia's force-align mask (`& !0xF`) is a deliberate emulator simplification.
+- **`RA0` semantics.** When `RA = 0`, base is literal zero; `lvebx VD, 0, RB` reads the byte at `RB` (and, in xenia, the surrounding aligned line).
+- **No update form.** No `lvebux` exists. Pointer-bumping requires a separate `addi`.
+- **No VMX128 sibling.** There is no `lvebx128` — the single-byte load family was kept Altivec-only in the Xbox 360 VMX128 extension, since 16-byte aligned loads (`lvx128`) plus `vperm`/`vsel` are usually faster.
+- **Common idiom.** Pair with `vperm` or `vsplt*` to broadcast the loaded byte to all lanes, or with `vinsertb` / shifts to assemble a vector from non-adjacent memory locations.
+
+## Related Instructions
+
+- [`lvehx`](lvehx.md), [`lvewx`](lvewx.md) — half-word and word element loads.
+- [`lvx`](lvx.md), [`lvxl`](lvxl.md) — full 16-byte aligned vector loads.
+- [`lvlx`](lvlx.md), [`lvrx`](lvrx.md) — load-left / load-right partial-vector ops for unaligned vector I/O.
+- [`stvebx`](stvebx.md) — symmetric single-byte store.
+
+## IBM Reference
+
+- [AIX 7.3 — `lvebx` (Load Vector Element Byte Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvebx-load-vector-element-byte-indexed-instruction)
+- `PowerISA v2.07B Book I` "Vector Facility" § "Vector Load and Store" for lane-placement rules.