chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/memory/lvewx.md
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migration/project-root/ppc-manual/memory/lvewx.md
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# `lvewx` — Load Vector Element Word Indexed
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> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00008e`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `lvewx` | `lvewx` | — | Load Vector Element Word Indexed |
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| `lvewx128` | `lvewx128` | — | Load Vector Element Word Indexed 128 |
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## Syntax
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```asm
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lvewx [VD], [RA0], [RB]
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lvewx128 [VD], [RA0], [RB]
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```
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## Encoding
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### `lvewx` — form `X`
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- **Opcode word:** `0x7c00008e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `71`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `lvewx128` — form `VX128_1`
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- **Opcode word:** `0x10000083`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `131`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `RA` | address register |
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| 16–20 | `RB` | offset register |
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| 21–27 | `XO` | extended opcode |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `—` | reserved |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA0` | lvewx: read; lvewx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `RB` | lvewx: read; lvewx128: read | Source GPR. |
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| `VD` | lvewx: write; lvewx128: write | Destination vector register. |
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## Register Effects
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### `lvewx`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `lvewx128`
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- **Reads (always):** `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`lvewx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvewx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:96`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L96)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:44`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L44)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:770`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L770)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1898-1913`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1898-L1913)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lvewx => {
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// Load a word from (EA & ~3) into vD at word slot
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// (EA & 0xF) >> 2. Other word lanes preserved (see lvebx).
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let base = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea_unaligned = base.wrapping_add(ctx.gpr[instr.rb()]) as u32;
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let ea = ea_unaligned & !0x3u32;
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let slot = ((ea_unaligned & 0xF) >> 2) as usize;
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let mut bytes = ctx.vr[instr.rd()].as_bytes();
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let w = mem.read_u32(ea);
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bytes[slot * 4] = (w >> 24) as u8;
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bytes[slot * 4 + 1] = (w >> 16) as u8;
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bytes[slot * 4 + 2] = (w >> 8) as u8;
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bytes[slot * 4 + 3] = (w & 0xFF) as u8;
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ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(bytes);
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ctx.pc += 4;
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}
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```
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</details>
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**`lvewx128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvewx128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:99`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L99)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:44`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L44)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:414`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L414)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3168-3174`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3168-L3174)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::lvewx128 => {
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let ea = ea_indexed(ctx, instr) & !0xF;
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let mut bytes = [0u8; 16];
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for i in 0..16 { bytes[i] = mem.read_u8(ea + i as u32); }
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ctx.vr[instr.vd128()] = xenia_types::Vec128::from_bytes(bytes);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Single word element load.** Architecturally `lvewx` loads exactly **four** bytes from `EA` (which must be 4-byte aligned) and places them in the word lane `(EA mod 16) >> 2` of the destination vector; the other 3 word lanes are *undefined*.
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- **EA must be word-aligned.** The low two bits of `EA` are masked by hardware. Xenia's shared snapshot rounds further to 16-byte alignment for both `lvewx` and `lvewx128`.
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- **Xenia simplification — full-line read.** Both `lvewx` and `lvewx128` snapshots load the full aligned 16 bytes from `ea & ~0xF` into the destination vector. Architectural undefined lanes are filled deterministically.
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- **`RA0` semantics.** When `RA = 0`, base is literal zero.
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- **No update form.** No `lvewux` exists.
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- **VMX128 sibling.** `lvewx128` shares semantics; the only difference is the operand encoding. VMX128 uses a 7-bit register index split across `VD128l ‖ VD128h` so it can address `v0..v127` instead of the 32-register Altivec space.
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- **Big-endian word within the lane.** The byte at the lower address is the most-significant byte of the word lane.
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- **Common idiom.** Pair with `vspltw` to broadcast the loaded word to all four lanes, or with `vperm` to gather words from sparse memory into one vector.
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## Related Instructions
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- [`lvebx`](lvebx.md), [`lvehx`](lvehx.md) — byte and half element loads.
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- [`lvx`](lvx.md), [`lvxl`](lvxl.md) — full 16-byte aligned vector loads.
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- [`lvlx`](lvlx.md), [`lvrx`](lvrx.md) — load-left / load-right partial-vector ops.
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- [`stvewx`](stvewx.md) — symmetric single-word store.
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## IBM Reference
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- [AIX 7.3 — `lvewx` (Load Vector Element Word Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvewx-load-vector-element-word-indexed-instruction)
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- `PowerISA v2.07B Book I` "Vector Facility" § "Vector Load and Store" for lane-placement rules; Microsoft XDK for `lvewx128`.
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