chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
260
migration/project-root/ppc-manual/memory/sth.md
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260
migration/project-root/ppc-manual/memory/sth.md
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# `sth` — Store Half Word
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> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xb0000000`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `sth` | `sth` | — | Store Half Word |
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| `sthu` | `sthu` | — | Store Half Word with Update |
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| `sthux` | `sthux` | — | Store Half Word with Update Indexed |
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| `sthx` | `sthx` | — | Store Half Word Indexed |
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## Syntax
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```asm
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sth [RS], [d]([RA0])
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sthu [RS], [d]([RA])
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sthux [RS], [RA], [RB]
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sthx [RS], [RA0], [RB]
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```
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## Encoding
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### `sth` — form `D`
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- **Opcode word:** `0xb0000000`
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- **Primary opcode (bits 0–5):** `44`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `sthu` — form `D`
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- **Opcode word:** `0xb4000000`
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- **Primary opcode (bits 0–5):** `45`
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- **Extended opcode:** —
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT` | destination GPR (or RS when storing) |
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| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
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| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
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### `sthux` — form `X`
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- **Opcode word:** `0x7c00036e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `439`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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### `sthx` — form `X`
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- **Opcode word:** `0x7c00032e`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `407`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RS` | sth: read; sthu: read; sthux: read; sthx: read | Source GPR (alias for RD in some stores). |
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| `RA0` | sth: read; sthx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
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| `d` | sth: read; sthu: read | 16-bit signed displacement (`d`) added to the base address register. |
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| `RA` | sthu: read; sthu: write; sthux: read; sthux: write | Source GPR (`r0`–`r31`). |
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| `RB` | sthux: read; sthx: read | Source GPR. |
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## Register Effects
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### `sth`
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- **Reads (always):** `RS`, `RA0`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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### `sthu`
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- **Reads (always):** `RS`, `RA`, `d`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `sthux`
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- **Reads (always):** `RS`, `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RA`
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- **Writes (conditional):** _none_
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### `sthx`
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- **Reads (always):** `RS`, `RA0`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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EA <- (RA|0) + EXTS(d)
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MEM(EA, 2) <- (RS)[48:63]
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`sth`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sth"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:455`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L455)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:73`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L73)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:367`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L367)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1363-1371`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1363-L1371)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::sth => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = ea.wrapping_add(instr.d() as i64 as u64) as u32;
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() { t.invalidate_for_write(ea); }
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}
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mem.write_u16(ea, ctx.gpr[instr.rs()] as u16);
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ctx.pc += 4;
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}
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```
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</details>
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**`sthu`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sthu"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:475`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L475)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:73`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L73)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:368`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L368)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1372-1380`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1372-L1380)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::sthu => {
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let ea = ctx.gpr[instr.ra()].wrapping_add(instr.d() as i64 as u64) as u32;
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() { t.invalidate_for_write(ea); }
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}
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mem.write_u16(ea, ctx.gpr[instr.rs()] as u16);
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ctx.gpr[instr.ra()] = ea as u64;
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ctx.pc += 4;
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}
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```
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</details>
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**`sthux`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sthux"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:485`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L485)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:73`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L73)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:808`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L808)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1390-1398`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1390-L1398)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::sthux => {
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let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() { t.invalidate_for_write(ea); }
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}
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mem.write_u16(ea, ctx.gpr[instr.rs()] as u16);
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ctx.gpr[instr.ra()] = ea as u64;
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ctx.pc += 4;
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}
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```
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</details>
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**`sthx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="sthx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:495`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L495)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:73`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L73)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:806`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L806)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1381-1389`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1381-L1389)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::sthx => {
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let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
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let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
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if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
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if t.has_active_reservers() { t.invalidate_for_write(ea); }
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}
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mem.write_u16(ea, ctx.gpr[instr.rs()] as u16);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Stores low 16 bits of `RS`.** Writes `(RS)[48:63]` — the low half-word — at `EA`. The xenia snapshot does `mem.write_u16(ea, ctx.gpr[instr.rs()] as u16)`. The high 48 bits of `RS` are ignored: storing a 64-bit value through `sth` silently truncates.
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- **Big-endian write.** Byte at `EA` is the high byte of the half (`RS[48:55]`), byte at `EA+1` is the low byte (`RS[56:63]`). On little-endian hosts the byte-swap happens at the memory boundary.
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- **`RA0` (non-update forms).** `RA = 0` in `sth` and `sthx` selects literal zero. Update forms `sthu` / `sthux` invoke `RA = 0` as an invalid form.
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- **Update-form post-write.** `sthu` / `sthux` write the computed `EA` back to `RA` after the store.
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- **No alignment requirement.** Xenon tolerates unaligned half-word stores; the two bytes are written at `EA` and `EA+1` regardless of alignment.
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- **Common in audio / Unicode code.** Standard store for 16-bit PCM samples and UTF-16 code units. Compilers emit `sth` for `short *` writes.
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- **Cache effects.** A `sth` to a cold line triggers a read-allocate; for bulk half-word writes to a fresh line, prefer pre-clearing with [`dcbz128`](dcbz.md).
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## Related Instructions
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- [`stb`](stb.md), [`stw`](stw.md), [`std`](std.md) — narrower / wider stores.
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- [`sthbrx`](sthbrx.md) — byte-reversed half-word store (little-endian half).
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- [`lhz`](lhz.md), [`lha`](lha.md) — corresponding loads (zero / sign extension).
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- [`stmw`](stmw.md), [`stswi`](stswi.md), [`stswx`](stswx.md) — bulk stores.
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## IBM Reference
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- [AIX 7.3 — `sth` (Store Half)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-sth-store-half-instruction)
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- [AIX 7.3 — `sthu` / `sthx` / `sthux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-sthu-store-half-update-instruction)
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Reference in New Issue
Block a user