chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

migration/project-root/ppc-manual/memory/stvehx.md

@@ -0,0 +1,138 @@
+# `stvehx` — Store Vector Element Half Word Indexed
+
+> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00014e`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `stvehx` | `stvehx` | — | Store Vector Element Half Word Indexed |
+
+## Syntax
+
+```asm
+stvehx [VS], [RA0], [RB]
+```
+
+## Encoding
+
+### `stvehx` — form `X`
+
+- **Opcode word:** `0x7c00014e`
+- **Primary opcode (bits 0–5):** `31`
+- **Extended opcode:** `167`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT/FRT/VRT` | destination |
+| 11–15 | `RA/FRA/VRA` | source A |
+| 16–20 | `RB/FRB/VRB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `Rc` | record-form flag |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+| `VS` | stvehx: read | Source vector register (alias for VD on stores). |
+| `RA0` | stvehx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
+| `RB` | stvehx: read | Source GPR. |
+
+## Register Effects
+
+### `stvehx`
+
+- **Reads (always):** `VS`, `RA0`, `RB`
+- **Reads (conditional):** _none_
+- **Writes (always):** _none_
+- **Writes (conditional):** _none_
+
+## Status-Register Effects
+
+_No condition-register or status-register effects._
+
+## Operation (pseudocode)
+
+```
+; Pseudocode derives directly from the xenia-rs interpreter
+; arm (see Implementation References). Operation semantics:
+;   - Read source operands from the fields listed under Operands.
+;   - Apply the arithmetic / logical / memory action described
+;     in the Description field above.
+;   - Write results to the destination register(s); update any
+;     status bits enumerated under Status-Register Effects.
+; Consult the IBM AIX reference link under IBM Reference for
+; canonical PPC-style pseudocode where xenia's expression is
+; terse.
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`stvehx`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvehx"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:160`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L160)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:77`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L77)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:784`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L784)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1927-1941`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1927-L1941)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::stvehx => {
+            // Store vS[slot] (1 halfword) at EA & ~1. slot = (EA & 0xF) >> 1.
+            let base = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
+            let ea_unaligned = base.wrapping_add(ctx.gpr[instr.rb()]) as u32;
+            let ea = ea_unaligned & !0x1u32;
+            // PPCBUG-512: stvehx was missing invalidate_for_write.
+            if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
+                if t.has_active_reservers() { t.invalidate_for_write(ea); }
+            }
+            let slot = ((ea_unaligned & 0xF) >> 1) as usize;
+            let bytes = ctx.vr[instr.rs()].as_bytes();
+            let h = ((bytes[slot * 2] as u16) << 8) | (bytes[slot * 2 + 1] as u16);
+            mem.write_u16(ea, h);
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **Single half-word element store.** Architecturally `stvehx` writes exactly **two** bytes from half-word lane `(EA mod 16) >> 1` of `VS` to address `EA & ~1` (low bit forced to half-aligned). Other lanes are unaffected, and bytes outside the 2-byte window are unaffected.
+- **Xenia simplification — full 16-byte write.** The xenia snapshot is shared with `stvebx` / `stvewx`: writes 16 bytes of the source vector at `ea & ~0xF`. This is stronger than the architectural 2-byte store — it overwrites 14 adjacent bytes that hardware would have left alone.
+- **EA forced half-aligned.** Hardware drops the low bit; xenia's shared snapshot drops the low four bits.
+- **`RA0` semantics.** `RA = 0` selects literal zero.
+- **No update form, no VMX128 sibling.** No `stvehux`; no `stvehx128`.
+- **Big-endian half within the lane.** The byte at the lower address is the most-significant byte of the half-word lane.
+- **Common idiom.** Pair with `vsplth` to broadcast then store one half; rare in compiled code (compilers prefer `sth`).
+
+## Related Instructions
+
+- [`stvebx`](stvebx.md), [`stvewx`](stvewx.md) — single byte / word element stores.
+- [`stvx`](stvx.md), [`stvxl`](stvxl.md) — full 16-byte aligned vector stores.
+- [`stvlx`](stvlx.md), [`stvrx`](stvrx.md) — store-left / store-right unaligned ops.
+- [`lvehx`](lvehx.md) — symmetric single-half load.
+
+## IBM Reference
+
+- [AIX 7.3 — `stvehx` (Store Vector Element Half Word Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stvehx-store-vector-element-half-word-indexed-instruction)
+- `PowerISA v2.07B Book I` "Vector Facility" § "Vector Load and Store".