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chore: add migration/ bundle for cross-machine setup

Browse Source 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
commit e6d43a23ac
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# `stwcx` — Store Word Conditional Indexed
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00012d`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stwcx` | `stwcx` | — | Store Word Conditional Indexed |
## Syntax
```asm
stwcx. [RS], [RA0], [RB]
```
## Encoding
### `stwcx` — form `X`
- **Opcode word:** `0x7c00012d`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `150`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RS` | stwcx: read | Source GPR (alias for RD in some stores). |
| `RA0` | stwcx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | stwcx: read | Source GPR. |
| `CR` | stwcx: write | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
## Register Effects
### `stwcx`
- **Reads (always):** `RS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `CR`
- **Writes (conditional):** _none_
## Status-Register Effects
- `stwcx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]` (always).
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`stwcx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stwcx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:868`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L868)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:81`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L81)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:782`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L782)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1225-1288`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1225-L1288)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::stwcx => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
let line = ea & !RESERVATION_MASK;
let table_route = ctx
.reservation_table
.as_ref()
.filter(|t| t.is_enabled())
.cloned();
// PPCBUG-151: stwcx. requires a word (lwarx) reservation;
// a doubleword (ldarx) reservation must not commit here.
let width_ok = ctx.reservation_width == 4;
let success = if let Some(t) = &table_route {
// Table-routed: success iff the slot still holds our
// reservation AND the per-ctx flag agrees (the per-ctx
// flag would be cleared by an intervening write or
// context switch).
ctx.has_reservation
&& width_ok
&& ctx.reserved_line == line
&& t.try_commit(ea, ctx.reserved_generation, ctx.hw_id)
} else {
// Legacy per-ctx path (M2 default / lockstep).
// PPCBUG-108: fires on non-primary HW slots under misconfig —
// if the table is disabled while workers are active, slots
// 1..N will trip this assert, surfacing the misconfiguration
// early in debug builds. Note: hw_id==0 (primary slot) taking
// this path while other slots run in parallel would NOT be
// caught; that case requires the table to be enabled instead.
debug_assert!(
ctx.hw_id == 0,
"PPCBUG-108: legacy per-ctx stwcx. on non-primary HW slot \
(hw_id={}) — ReservationTable must be enabled under --parallel",
ctx.hw_id
);
ctx.has_reservation && width_ok && ctx.reserved_line == line
};
if success {
mem.write_u32(ea, ctx.gpr[instr.rs()] as u32);
ctx.cr[0] = crate::context::CrField {
lt: false,
gt: false,
eq: true,
so: ctx.xer_so != 0,
};
} else {
ctx.cr[0] = crate::context::CrField {
lt: false,
gt: false,
eq: false,
so: ctx.xer_so != 0,
};
// Failed stwcx: if we held the reservation in the table
// (someone else displaced our gen), release it from the
// counter so `has_active_reservers` returns to zero
// when no real reserver exists.
if let Some(t) = &table_route {
t.release(ea, ctx.reserved_generation, ctx.hw_id);
}
}
ctx.has_reservation = false;
ctx.reservation_width = 0; // PPCBUG-151: always clear on exit
ctx.pc += 4;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Always sets `Rc=1` (the trailing dot).** The mnemonic is `stwcx.` — there is no non-Rc variant. CR0 is updated unconditionally to communicate success/failure. `EQ=1` means the conditional store succeeded; `EQ=0` means it failed (the prior reservation was lost; no memory write).
- **Reservation check.** Xenia's snapshot tests `has_reservation && reserved_addr == ea`. On match it performs `mem.write_u32` (low 32 bits of `RS`, big-endian), sets `EQ=1`. On mismatch, no memory write and `EQ=0`. In both cases the reservation is cleared, so a retry must begin with a fresh [`lwarx`](lwarx.md).
- **Hardware granule.** PowerISA defines reservation by aligned word; Xenon implementations widen this to one 128-byte cache line. A store by another agent anywhere in the line clears the reservation. Xenia's per-address check is more permissive than hardware.
- **Alignment requirement.** `EA` must be 4-byte aligned. Unaligned `stwcx.` raises an alignment exception on real hardware; xenia does not check.
- **`RA0` semantics.** When `RA = 0`, base is literal zero — `stwcx. RS, 0, RB` writes at exact `RB`.
- **CR0[SO] reflects XER[SO].** Like all CR-updating ops, CR0[SO] is copied from `XER[SO]` rather than computed.
- **Spurious failures permitted.** Hardware may report failure even when no actual conflict occurred (e.g. on context switch). Application code treats failure as a normal retry condition.
- **Pair atomically with [`lwarx`](lwarx.md).** Don't interleave loads/stores between the pair; an [`lwsync`](sync.md) inside the loop body is common.
- **Stores low 32 bits of `RS`.** The high 32 bits of the source GPR are ignored.
## Related Instructions
- [`lwarx`](lwarx.md) — load-and-reserve word (the matching load).
- [`stdcx`](stdcx.md) / [`ldarx`](ldarx.md) — 64-bit reservation pair.
- [`stw`](stw.md), [`stwx`](stw.md) — non-conditional word stores.
- [`sync`](sync.md), [`lwsync`](sync.md), [`isync`](isync.md) — barriers used around reservation pairs.
## IBM Reference
- [AIX 7.3 — `stwcx.` (Store Word Conditional Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stwcx-store-word-conditional-indexed-instruction)
- `PowerISA v2.07B Book II` § "Atomic Update Primitives" for canonical reservation semantics and granule rules.