chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/vmx/vaddfp.md
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migration/project-root/ppc-manual/vmx/vaddfp.md
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# `vaddfp` — Vector Add Floating Point
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000000a`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vaddfp` | `vaddfp` | — | Vector Add Floating Point |
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| `vaddfp128` | `vaddfp128` | — | Vector128 Add Floating Point |
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## Syntax
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```asm
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vaddfp [VD], [VA], [VB]
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vaddfp128 [VD], [VA], [VB]
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```
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## Encoding
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### `vaddfp` — form `VX`
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- **Opcode word:** `0x1000000a`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `10`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vaddfp128` — form `VX128`
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- **Opcode word:** `0x14000010`
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- **Primary opcode (bits 0–5):** `5`
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- **Extended opcode:** `16`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vaddfp: read; vaddfp128: read | Source A vector register. |
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| `VB` | vaddfp: read; vaddfp128: read | Source B vector register. |
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| `VD` | vaddfp: write; vaddfp128: write | Destination vector register. |
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## Register Effects
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### `vaddfp`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vaddfp128`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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for each 32-bit float lane i in 0..3:
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VD[i] <- VA[i] + VB[i]
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```
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## C Translation Example
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```c
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/* vaddfp VD, VA, VB — lane-wise float add */
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for (int i = 0; i < 4; ++i) v[insn.VD].f[i] = v[insn.VA].f[i] + v[insn.VB].f[i];
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```
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## Implementation References
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**`vaddfp`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vaddfp"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:341`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L341)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:89`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L89)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:438`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L438)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1984-1998`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1984-L1998)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vaddfp => {
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// PPCBUG-435: VSCR.NJ=1 (Xbox 360 always boots with this set) requires
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// flush-to-zero on subnormal inputs and outputs. Canary VMX float
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// arithmetic flushes denormals unconditionally.
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let a = ctx.vr[instr.ra()].as_f32x4();
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let b = ctx.vr[instr.rb()].as_f32x4();
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let mut r = [0f32; 4];
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for i in 0..4 {
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let ai = vmx::flush_denorm(a[i]);
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let bi = vmx::flush_denorm(b[i]);
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r[i] = vmx::flush_denorm(ai + bi);
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}
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ctx.vr[instr.rd()] = xenia_types::Vec128::from_f32x4_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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**`vaddfp128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vaddfp128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:344`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L344)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:89`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L89)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:610`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L610)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1999-2011`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1999-L2011)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vaddfp128 => {
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// PPCBUG-435: same as vaddfp.
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let a = ctx.vr[instr.va128()].as_f32x4();
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let b = ctx.vr[instr.vb128()].as_f32x4();
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let mut r = [0f32; 4];
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for i in 0..4 {
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let ai = vmx::flush_denorm(a[i]);
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let bi = vmx::flush_denorm(b[i]);
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r[i] = vmx::flush_denorm(ai + bi);
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}
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ctx.vr[instr.vd128()] = xenia_types::Vec128::from_f32x4_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Extended Pseudocode
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```
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; Four independent lane-wise IEEE-754 single-precision adds
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for i in 0..3:
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VD[i] <- VA[i] + VB[i] ; binary32, rounded to nearest
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; No FPSCR update (VMX uses VSCR, which only has NJ / SAT — and vaddfp doesn't saturate)
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```
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## Special Cases & Edge Conditions
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- **Lane indexing is big-endian.** Lane 0 is the **most significant** 4 bytes of the 128-bit register (the one that appears at the lowest byte offset after a `stvx`). Xenia's `Vec128::as_f32x4()` already reads lanes in PPC order on x86-64. When writing C that manipulates individual lanes, index `v.f[0]` as "the byte 0..3" of the big-endian layout.
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- **Flush-denormals ("NJ") mode.** Altivec is independent of FPSCR — it has its own 2-bit VSCR (`NJ` for non-Java mode + `SAT` sticky-saturation). VMX float operations honour `VSCR[NJ]`: when set (the Xenon boot default), denormal inputs and outputs are flushed to zero. This is **opposite** to the scalar FPU, which has its own non-IEEE bit. Xenia sets `NJ = 1` at context creation ([`context.rs`](../../xenia-rs/crates/xenia-cpu/src/context.rs)).
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- **No exception, no trap.** Altivec floats never raise exceptions. NaN inputs produce NaN outputs; `±∞ − ±∞` yields a NaN; there is no VXISI-style status bit. `VSCR[SAT]` is **not** touched by `vaddfp` (it saturates integer ops, not floats).
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- **Four independent lanes.** Each lane's operation is unaffected by the others. Aliasing between `VA`, `VB`, and `VD` is legal and common (`vaddfp v3, v3, v4`).
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- **VMX128 sibling (`vaddfp128`).** Semantics identical; only the register encoding differs. VMX128 uses a 7-bit operand ID per source (and destination) built from two or three non-contiguous bit fields — see [`categories/vmx128.md`](../categories/vmx128.md). Any bit pattern encodable as a 32-register VX-form is also encodable as a VMX128 form, so compilers picked the more compact form that reached the needed register range.
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- **On x86-64 hosts.** A natural compilation uses `_mm_add_ps` or AVX `vaddps`. These preserve lane indexing because PPC lane 0 maps to x86 lane 3 only if you treat the 128-bit value as "big-endian in memory" — i.e. byte-swap on load/store. With xenia's `_be` memory helpers, `_mm_add_ps` gives the right per-lane result.
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## Related Instructions
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- [`vsubfp`](vsubfp.md) — lane-wise float subtract.
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- [`vmaddfp`](vmaddfp.md) — lane-wise `(VA × VC) + VB` (fused multiply-add with single rounding).
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- [`vnmsubfp`](vnmsubfp.md) — `−((VA × VC) − VB)`.
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- [`vmaxfp`](vmaxfp.md), [`vminfp`](vminfp.md) — IEEE-754-aware max/min (NaN propagation).
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- [`vcmpeqfp`](vcmpeqfp.md), [`vcmpgtfp`](vcmpgtfp.md), [`vcmpgefp`](vcmpgefp.md), [`vcmpbfp`](vcmpbfp.md) — compares producing per-lane all-ones / all-zero masks.
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- [`vrfin`](vrfin.md), [`vrfim`](vrfim.md), [`vrfip`](vrfip.md), [`vrfiz`](vrfiz.md) — round to integer (to-nearest / down / up / toward-zero).
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- [`vmulfp`](vmulfp.md) — xenia's helper; not a native Altivec op, included for convenience. Hardware games use `vmaddfp v, va, vc, v0_zero` instead.
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## IBM Reference
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- [AIX 7.3 — `vaddfp` (Vector Add Floating Point)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vaddfp-vector-add-floating-point-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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