chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/vmx/vcmpgtsh.md
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migration/project-root/ppc-manual/vmx/vcmpgtsh.md
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# `vcmpgtsh` — Vector Compare Greater-Than Signed Half Word
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x10000346`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vcmpgtsh` | `vcmpgtsh` | — | Vector Compare Greater-Than Signed Half Word |
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| `vcmpgtsh.` | `vcmpgtsh` | Rc=1 | Vector Compare Greater-Than Signed Half Word |
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## Syntax
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```asm
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vcmpgtsh[Rc] [VD], [VA], [VB]
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```
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## Encoding
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### `vcmpgtsh` — form `VC`
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- **Opcode word:** `0x10000346`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `838`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT` | destination vector register |
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| 11–15 | `VRA` | source A |
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| 16–20 | `VRB` | source B |
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| 21 | `Rc` | record-form flag (updates CR6) |
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| 22–31 | `XO` | extended opcode (10 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vcmpgtsh: read | Source A vector register. |
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| `VB` | vcmpgtsh: read | Source B vector register. |
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| `VD` | vcmpgtsh: write | Destination vector register. |
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| `CR` | vcmpgtsh: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `vcmpgtsh`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `vcmpgtsh`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vcmpgtsh`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpgtsh"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:739`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L739)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:97`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L97)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:567`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L567)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3788-3800`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3788-L3800)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vcmpgtsh => {
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let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
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let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
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let mut r = [0u16; 8];
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for i in 0..8 { r[i] = if a[i] > b[i] { 0xFFFF } else { 0 }; }
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let v = xenia_types::Vec128::from_u16x8_array(r);
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if instr.vc_rc_bit() {
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let (t, f) = crate::vmx::cr6_flags_from_mask(v);
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ctx.cr[6] = crate::context::CrField { lt: t, gt: false, eq: f, so: false };
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}
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ctx.vr[instr.rd()] = v;
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Per-half mask: all-ones / all-zero.** Eight half-word lanes; `VD[i] = (int16(VA[i]) > int16(VB[i])) ? 0xFFFF : 0x0000`. Lane 0 is the most-significant half.
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- **Sign matters.** `0x8000 > 0x0001` is `true` unsigned but `false` signed (`-32768 > 1`). Pick `vcmpgtsh` deliberately when sign bit affects ordering.
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- **CR6 update when `Rc=1`** (`vcmpgtsh.`). CR6 = `[lt = all-true, gt = 0, eq = all-false, so = 0]`.
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- **Compose with `vsel`.** Mask drives [`vsel`](vsel.md) per half.
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- **Common usage.** Q15 audio threshold detection, signed image-processing kernels.
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- **No `VSCR` interaction, no XER, no traps.**
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- **Aliasing legal.**
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- **No VMX128 sibling.**
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## Related Instructions
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- [`vcmpgtuh`](vcmpgtuh.md) — same width, unsigned `>`.
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- [`vcmpequh`](vcmpequh.md) — equality at half width.
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- [`vcmpgtsb`](vcmpgtsb.md), [`vcmpgtsw`](vcmpgtsw.md) — signed `>` at byte / word width.
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- [`vsel`](vsel.md), [`vand`](vand.md), [`vandc`](vandc.md), [`vor`](vor.md), [`vxor`](vxor.md) — mask consumers / combinators.
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- [`vmaxsh`](vmaxsh.md), [`vminsh`](vminsh.md) — direct signed max / min.
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## IBM Reference
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- [AIX 7.3 — `vcmpgtsh` (Vector Compare Greater-Than Signed Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vcmpgtsh-vector-compare-greater-than-signed-half-word-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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