chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

migration/project-root/ppc-manual/vmx/vcmpgtub.md

@@ -0,0 +1,140 @@
+# `vcmpgtub` — Vector Compare Greater-Than Unsigned Byte
+
+> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x10000206`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `vcmpgtub` | `vcmpgtub` | — | Vector Compare Greater-Than Unsigned Byte |
+| `vcmpgtub.` | `vcmpgtub` | Rc=1 | Vector Compare Greater-Than Unsigned Byte |
+
+## Syntax
+
+```asm
+vcmpgtub[Rc] [VD], [VA], [VB]
+```
+
+## Encoding
+
+### `vcmpgtub` — form `VC`
+
+- **Opcode word:** `0x10000206`
+- **Primary opcode (bits 0–5):** `4`
+- **Extended opcode:** `518`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode (4) |
+| 6–10 | `VRT` | destination vector register |
+| 11–15 | `VRA` | source A |
+| 16–20 | `VRB` | source B |
+| 21 | `Rc` | record-form flag (updates CR6) |
+| 22–31 | `XO` | extended opcode (10 bits) |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+| `VA` | vcmpgtub: read | Source A vector register. |
+| `VB` | vcmpgtub: read | Source B vector register. |
+| `VD` | vcmpgtub: write | Destination vector register. |
+| `CR` | vcmpgtub: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
+
+## Register Effects
+
+### `vcmpgtub`
+
+- **Reads (always):** `VA`, `VB`
+- **Reads (conditional):** _none_
+- **Writes (always):** `VD`
+- **Writes (conditional):** `CR`
+
+## Status-Register Effects
+
+- `vcmpgtub`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
+
+## Operation (pseudocode)
+
+```
+; Pseudocode derives directly from the xenia-rs interpreter
+; arm (see Implementation References). Operation semantics:
+;   - Read source operands from the fields listed under Operands.
+;   - Apply the arithmetic / logical / memory action described
+;     in the Description field above.
+;   - Write results to the destination register(s); update any
+;     status bits enumerated under Status-Register Effects.
+; Consult the IBM AIX reference link under IBM Reference for
+; canonical PPC-style pseudocode where xenia's expression is
+; terse.
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`vcmpgtub`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpgtub"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:747`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L747)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:97`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L97)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:562`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L562)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3749-3761`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3749-L3761)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::vcmpgtub => {
+            let a = ctx.vr[instr.ra()].as_bytes();
+            let b = ctx.vr[instr.rb()].as_bytes();
+            let mut r = [0u8; 16];
+            for i in 0..16 { r[i] = if a[i] > b[i] { 0xFF } else { 0 }; }
+            let v = xenia_types::Vec128::from_bytes(r);
+            if instr.vc_rc_bit() {
+                let (t, f) = crate::vmx::cr6_flags_from_mask(v);
+                ctx.cr[6] = crate::context::CrField { lt: t, gt: false, eq: f, so: false };
+            }
+            ctx.vr[instr.rd()] = v;
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **Per-byte mask: all-ones / all-zero.** Sixteen byte lanes; `VD[i] = (uint8(VA[i]) > uint8(VB[i])) ? 0xFF : 0x00`. Lane 0 is the most-significant byte after `stvx`.
+- **Sign matters.** `0xFF > 0x01` is `true` unsigned but `false` signed (`-1 > 1`); pick `vcmpgtub` only when both sides should be treated as `0..255`.
+- **CR6 update when `Rc=1`** (`vcmpgtub.`). CR6 = `[lt = all-true, gt = 0, eq = all-false, so = 0]` — built by xenia's `crate::vmx::cr6_flags_from_mask`.
+- **Compose with `vsel`.** Mask drives [`vsel`](vsel.md) per byte.
+- **Common usage.** Pixel "brighter than" tests, byte-level histogramming, threshold-based binarisation.
+- **No `VSCR` interaction, no XER, no traps.**
+- **Aliasing legal.**
+- **No VMX128 sibling.**
+
+## Related Instructions
+
+- [`vcmpgtsb`](vcmpgtsb.md) — same width, signed `>`.
+- [`vcmpequb`](vcmpequb.md) — equality at byte width.
+- [`vcmpgtuh`](vcmpgtuh.md), [`vcmpgtuw`](vcmpgtuw.md) — unsigned `>` at half / word width.
+- [`vsel`](vsel.md), [`vand`](vand.md), [`vandc`](vandc.md), [`vor`](vor.md), [`vxor`](vxor.md) — mask consumers / combinators.
+- [`vmaxub`](vmaxub.md), [`vminub`](vminub.md) — direct unsigned max / min.
+
+## IBM Reference
+
+- [AIX 7.3 — `vcmpgtub` (Vector Compare Greater-Than Unsigned Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vcmpgtub-vector-compare-greater-than-unsigned-byte-instruction)
+- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)