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chore: add migration/ bundle for cross-machine setup

Browse Source 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
commit e6d43a23ac
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# `vmladduhm` — Vector Multiply-Low and Add Unsigned Half Word Modulo
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000022`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmladduhm` | `vmladduhm` | — | Vector Multiply-Low and Add Unsigned Half Word Modulo |
## Syntax
```asm
vmladduhm [VD], [VA], [VB], [VC]
```
## Encoding
### `vmladduhm` — form `VA`
- **Opcode word:** `0x10000022`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `34`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmladduhm: read | Source A vector register. |
| `VB` | vmladduhm: read | Source B vector register. |
| `VC` | vmladduhm: read | Source C vector register / 3-bit selector. |
| `VD` | vmladduhm: write | Destination vector register. |
## Register Effects
### `vmladduhm`
- **Reads (always):** `VA`, `VB`, `VC`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vmladduhm`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmladduhm"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:951`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L951)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:104`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L104)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:578`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L578)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3549-3560`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3549-L3560)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vmladduhm => {
// Multiply-low add (modulo): vD[i] = u16(vA[i] * vB[i] + vC[i]).
let a = ctx.vr[instr.ra()].as_u16x8();
let b = ctx.vr[instr.rb()].as_u16x8();
let c = ctx.vr[instr.rc()].as_u16x8();
let mut r = [0u16; 8];
for i in 0..8 {
r[i] = a[i].wrapping_mul(b[i]).wrapping_add(c[i]);
}
ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
ctx.pc += 4;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Modulo multiply-low add.** Eight half-word lanes; per lane:
```
VD[i] = (uint16(VA[i]) * uint16(VB[i]) + uint16(VC[i])) mod 2^16
```
Only the **low** 16 bits of the 32-bit product survive — the "ml" in the mnemonic = "multiply low" (versus `vmh*` for "multiply high"). This is the fastest of the multiply-add family because nothing saturates and nothing rounds.
- **Sign-agnostic.** Modulo multiply for signed `int16` and unsigned `u16` is bit-identical at the low 16 bits, so this single instruction serves both.
- **No `VSCR[SAT]` change.** Wrap is silent.
- **No XER, no exceptions.**
- **Big-endian half lanes.** Lane 0 is the most-significant half.
- **Aliasing legal.** `vmladduhm v3, v3, v4, v3` is the standard accumulate idiom (same register as both `VA` and `VC`).
- **No VMX128 sibling.**
- **Common usage.** Stride / index computation in vector loops, RGBA8 component recombination after a [`vupkhsb`](vupkhsb.md), per-element polynomial evaluation at half precision.
## Related Instructions
- [`vmhaddshs`](vmhaddshs.md) — saturating high-half signed multiply-add (Q15).
- [`vmhraddshs`](vmhraddshs.md) — same, with rounding.
- [`vmsumuhm`](vmsumuhm.md), [`vmsummbm`](vmsummbm.md) — multiply-sum across pairs of lanes.
- [`vadduhm`](vadduhm.md), [`vmaxuh`](vmaxuh.md) — companion modulo / max ops at half width.
## IBM Reference
- [AIX 7.3 — `vmladduhm` (Vector Multiply-Low and Add Unsigned Half Word Modulo)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmladduhm-vector-multiply-low-add-unsigned-half-word-modulo-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Add Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)