chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/vmx/vmsumshm.md
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# `vmsumshm` — Vector Multiply-Sum Signed Half Word Modulo
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000028`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vmsumshm` | `vmsumshm` | — | Vector Multiply-Sum Signed Half Word Modulo |
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## Syntax
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```asm
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vmsumshm [VD], [VA], [VB], [VC]
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```
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## Encoding
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### `vmsumshm` — form `VA`
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- **Opcode word:** `0x10000028`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `40`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT` | destination vector register |
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| 11–15 | `VRA` | source A |
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| 16–20 | `VRB` | source B |
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| 21–25 | `VRC` | source C / shift |
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| 26–31 | `XO` | extended opcode (6 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vmsumshm: read | Source A vector register. |
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| `VB` | vmsumshm: read | Source B vector register. |
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| `VC` | vmsumshm: read | Source C vector register / 3-bit selector. |
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| `VD` | vmsumshm: write | Destination vector register. |
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## Register Effects
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### `vmsumshm`
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- **Reads (always):** `VA`, `VB`, `VC`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vmsumshm`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsumshm"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1042`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1042)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:107`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L107)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:583`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L583)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3625-3638`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3625-L3638)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vmsumshm => {
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let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
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let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
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let c = crate::vmx::as_i32x4(ctx.vr[instr.rc()]);
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let mut r = [0i32; 4];
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for i in 0..4 {
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let s = (a[2*i] as i32 * b[2*i] as i32)
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.wrapping_add(a[2*i+1] as i32 * b[2*i+1] as i32)
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.wrapping_add(c[i]);
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r[i] = s;
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}
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ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Signed half-word multiply-sum, modulo.** Per word lane:
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```
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VD[i] = (VC[i] + int16(VA[2*i]) * int16(VB[2*i])
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+ int16(VA[2*i+1]) * int16(VB[2*i+1])) mod 2^32
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```
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Two signed-half × signed-half products plus a signed-word accumulator → one signed word per output lane.
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- **Modulo wrap, never saturates.** **`VSCR[SAT]` is not touched** — wraparound silently. Use [`vmsumshs`](vmsumshs.md) for the saturating variant.
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- **Big-endian half lanes.** Lane 0 is the most-significant half; output word `i` consumes halves `2*i` and `2*i+1`.
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- **No XER, no exceptions.**
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- **Aliasing legal.**
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- **No VMX128 sibling.**
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- **Common usage.** Q15 dot products of paired audio samples, 2-tap signed FIR coefficients.
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## Related Instructions
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- [`vmsumshs`](vmsumshs.md) — same shape with saturating output.
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- [`vmsumuhm`](vmsumuhm.md) / [`vmsumuhs`](vmsumuhs.md) — unsigned half multiply-sum.
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- [`vmsumubm`](vmsumubm.md), [`vmsummbm`](vmsummbm.md) — multiply-sum at byte width.
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- [`vmhaddshs`](vmhaddshs.md), [`vmhraddshs`](vmhraddshs.md) — per-lane multiply-add (no horizontal reduction).
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- [`vsum2sws`](vsum2sws.md), [`vsumsws`](vsumsws.md) — pure horizontal sums.
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## IBM Reference
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- [AIX 7.3 — `vmsumshm` (Vector Multiply-Sum Signed Half Word Modulo)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmsumshm-vector-multiply-sum-signed-half-word-modulo-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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