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chore: add migration/ bundle for cross-machine setup

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Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
commit e6d43a23ac
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# `vmsumuhm` — Vector Multiply-Sum Unsigned Half Word Modulo
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000026`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmsumuhm` | `vmsumuhm` | — | Vector Multiply-Sum Unsigned Half Word Modulo |
## Syntax
```asm
vmsumuhm [VD], [VA], [VB], [VC]
```
## Encoding
### `vmsumuhm` — form `VA`
- **Opcode word:** `0x10000026`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `38`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmsumuhm: read | Source A vector register. |
| `VB` | vmsumuhm: read | Source B vector register. |
| `VC` | vmsumuhm: read | Source C vector register / 3-bit selector. |
| `VD` | vmsumuhm: write | Destination vector register. |
## Register Effects
### `vmsumuhm`
- **Reads (always):** `VA`, `VB`, `VC`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vmsumuhm`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsumuhm"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1057`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1057)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:107`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L107)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:581`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L581)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3595-3608`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3595-L3608)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vmsumuhm => {
let a = ctx.vr[instr.ra()].as_u16x8();
let b = ctx.vr[instr.rb()].as_u16x8();
let c = ctx.vr[instr.rc()].as_u32x4();
let mut r = [0u32; 4];
for i in 0..4 {
let s = (a[2*i] as u32 * b[2*i] as u32)
.wrapping_add(a[2*i+1] as u32 * b[2*i+1] as u32)
.wrapping_add(c[i]);
r[i] = s;
}
ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
ctx.pc += 4;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Unsigned half-word multiply-sum, modulo.** Per word lane:
```
VD[i] = (VC[i] + uint16(VA[2*i]) * uint16(VB[2*i])
+ uint16(VA[2*i+1]) * uint16(VB[2*i+1])) mod 2^32
```
Two unsigned-half × unsigned-half products and an unsigned-word accumulator → one unsigned word per output lane.
- **Modulo wrap, never saturates.** **`VSCR[SAT]` is not touched.**
- **Big-endian half lanes.** Lane 0 is the most-significant half.
- **No XER, no exceptions.**
- **Aliasing legal.**
- **No VMX128 sibling.**
- **Common usage.** Unsigned 16-bit FIR taps; pair-wise component sums for half-precision colour data.
## Related Instructions
- [`vmsumuhs`](vmsumuhs.md) — same shape, saturating output.
- [`vmsumshm`](vmsumshm.md) / [`vmsumshs`](vmsumshs.md) — signed half multiply-sum.
- [`vmsumubm`](vmsumubm.md), [`vmsummbm`](vmsummbm.md) — multiply-sum at byte width.
- [`vmladduhm`](vmladduhm.md) — per-lane multiply-add at half width.
## IBM Reference
- [AIX 7.3 — `vmsumuhm` (Vector Multiply-Sum Unsigned Half Word Modulo)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmsumuhm-vector-multiply-sum-unsigned-half-word-modulo-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)