chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/vmx/vmulosb.md
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migration/project-root/ppc-manual/vmx/vmulosb.md
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# `vmulosb` — Vector Multiply Odd Signed Byte
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000108`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vmulosb` | `vmulosb` | — | Vector Multiply Odd Signed Byte |
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## Syntax
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```asm
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vmulosb [VD], [VA], [VB]
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```
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## Encoding
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### `vmulosb` — form `VX`
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- **Opcode word:** `0x10000108`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `264`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vmulosb: read | Source A vector register. |
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| `VB` | vmulosb: read | Source B vector register. |
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| `VD` | vmulosb: write | Destination vector register. |
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## Register Effects
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### `vmulosb`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vmulosb`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmulosb"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1106`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1106)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:109`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L109)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:456`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L456)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3477-3484`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3477-L3484)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vmulosb => {
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let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
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let b = crate::vmx::as_i8x16(ctx.vr[instr.rb()]);
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let mut r = [0i16; 8];
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for i in 0..8 { r[i] = a[2 * i + 1] as i16 * b[2 * i + 1] as i16; }
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ctx.vr[instr.rd()] = crate::vmx::from_i16x8(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Odd-lane signed-byte multiply.** Only the odd-indexed byte lanes (1, 3, 5, 7, 9, 11, 13, 15 — big-endian numbering) of `VA` and `VB` participate. Each pair is treated as signed 8-bit, multiplied, and sign-extended to a signed 16-bit result in the corresponding half-word of `VD`. Pairing: `VD.h[i] = (int8)VA.b[2*i+1] * (int8)VB.b[2*i+1]` for `i ∈ 0..7`.
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- **Lane-count reduction.** 16 byte lanes → 8 half-word lanes.
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- **No overflow.** `(-128) * (-128) = 0x4000`, `(127) * (127) = 0x3F01` — both fit in int16. `VSCR[SAT]` is **not** set.
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- **Pair with [`vmulesb`](vmulesb.md)** to get every signed byte × byte product; interleave via `vmrghh`/`vmrglh`, or feed into [`vmsummbm`](vmsummbm.md) for a multiply-accumulate.
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- **Signed vs. unsigned distinction.** The `s` in `vmulosb` makes the product arithmetic: negative operands sign-extend. Compare with [`vmuloub`](vmuloub.md) which zero-extends.
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- **No `Rc`, no XER, no VSCR side-effect.** No VMX128 sibling.
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## Related Instructions
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- [`vmulesb`](vmulesb.md) — even-lane signed byte multiply.
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- [`vmuloub`](vmuloub.md), [`vmuleub`](vmuleub.md) — unsigned byte twins.
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- [`vmulosh`](vmulosh.md), [`vmulesh`](vmulesh.md) — signed half-word even/odd.
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- [`vmsummbm`](vmsummbm.md) — fused signed-byte multiply-sum modulo.
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- [`vmrghh`](vmrghh.md), [`vmrglh`](vmrglh.md) — interleave the even/odd half-word results.
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## IBM Reference
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- [AIX 7.3 — `vmulosb` (Vector Multiply Odd Signed Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmulosb-vector-multiply-odd-signed-byte-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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