chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/vmx/vpkswus.md
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migration/project-root/ppc-manual/vmx/vpkswus.md
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# `vpkswus` — Vector Pack Signed Word Unsigned Saturate
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000014e`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vpkswus` | `vpkswus` | — | Vector Pack Signed Word Unsigned Saturate |
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| `vpkswus128` | `vpkswus128` | — | Vector128 Pack Signed Word Unsigned Saturate |
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## Syntax
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```asm
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vpkswus [VD], [VA], [VB]
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vpkswus128 [VD], [VA], [VB]
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```
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## Encoding
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### `vpkswus` — form `VX`
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- **Opcode word:** `0x1000014e`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `334`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vpkswus128` — form `VX128`
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- **Opcode word:** `0x140002c0`
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- **Primary opcode (bits 0–5):** `5`
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- **Extended opcode:** `704`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vpkswus: read; vpkswus128: read | Source A vector register. |
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| `VB` | vpkswus: read; vpkswus128: read | Source B vector register. |
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| `VD` | vpkswus: write; vpkswus128: write | Destination vector register. |
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| `VSCR` | vpkswus: write; vpkswus128: write | Vector Status and Control Register (NJ/SAT bits). |
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## Register Effects
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### `vpkswus`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`, `VSCR`
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- **Writes (conditional):** _none_
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### `vpkswus128`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`, `VSCR`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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- `vpkswus`: **VSCR[SAT]** may be stickied on saturating vector operations.
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- `vpkswus128`: **VSCR[SAT]** may be stickied on saturating vector operations.
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vpkswus`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkswus"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1889`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1889)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:114`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L114)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:465`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L465)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4096-4108`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4096-L4108)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vpkswus | PpcOpcode::vpkswus128 => {
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let is_128 = matches!(instr.opcode, PpcOpcode::vpkswus128);
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let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
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else { (instr.ra(), instr.rb(), instr.rd()) };
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let a = crate::vmx::as_i32x4(ctx.vr[ra]);
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let b = crate::vmx::as_i32x4(ctx.vr[rb]);
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let mut r = [0u16; 8]; let mut sat = false;
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for i in 0..4 { let (v, s) = crate::vmx::sat_i32_to_u16(a[i]); r[i] = v; sat |= s; }
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for i in 0..4 { let (v, s) = crate::vmx::sat_i32_to_u16(b[i]); r[4 + i] = v; sat |= s; }
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if sat { ctx.set_vscr_sat(true); }
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ctx.vr[rd] = xenia_types::Vec128::from_u16x8_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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**`vpkswus128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkswus128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1892`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1892)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:114`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L114)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:624`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L624)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4096-4108`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4096-L4108)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vpkswus | PpcOpcode::vpkswus128 => {
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let is_128 = matches!(instr.opcode, PpcOpcode::vpkswus128);
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let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
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else { (instr.ra(), instr.rb(), instr.rd()) };
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let a = crate::vmx::as_i32x4(ctx.vr[ra]);
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let b = crate::vmx::as_i32x4(ctx.vr[rb]);
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let mut r = [0u16; 8]; let mut sat = false;
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for i in 0..4 { let (v, s) = crate::vmx::sat_i32_to_u16(a[i]); r[i] = v; sat |= s; }
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for i in 0..4 { let (v, s) = crate::vmx::sat_i32_to_u16(b[i]); r[4 + i] = v; sat |= s; }
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if sat { ctx.set_vscr_sat(true); }
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ctx.vr[rd] = xenia_types::Vec128::from_u16x8_array(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Signed word → unsigned half-word saturating pack.** Each of the 8 input word lanes is interpreted as `int32` and clamped to `[0, 65535]`. Negatives → 0, values above 65535 → 65535, sticky-setting `VSCR[SAT]`.
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- **Lane-count doubling.** 8 word lanes → 8 half-word lanes, ordered as `VA` then `VB`.
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- **Choose over [`vpkswss`](vpkswss.md)** when negative results shouldn't survive — e.g. clamped colour or intensity values that happen to have arrived in `int32` form.
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- **`VSCR[SAT]` is sticky.**
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- **No `Rc`, no XER / FPSCR.**
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- **VMX128 sibling [`vpkswus128`](vpkswus128.md).**
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## Related Instructions
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- [`vpkswss`](vpkswss.md) — signed → signed clamp.
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- [`vpkuwus`](vpkuwus.md) — unsigned word input → unsigned half-word.
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- [`vpkuwum`](vpkuwum.md) — modulo (truncate) pack.
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- [`vpkshus`](vpkshus.md) — the half-word → byte analogue.
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- [`vupkhsh`](vupkhsh.md), [`vupklsh`](vupklsh.md) — signed-half-word unpacks.
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## IBM Reference
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- [AIX 7.3 — `vpkswus` (Vector Pack Signed Word Unsigned Saturate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vpkswus-vector-pack-signed-word-unsigned-saturate-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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