chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/vmx/vpkuhum.md
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migration/project-root/ppc-manual/vmx/vpkuhum.md
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# `vpkuhum` — Vector Pack Unsigned Half Word Unsigned Modulo
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000000e`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vpkuhum` | `vpkuhum` | — | Vector Pack Unsigned Half Word Unsigned Modulo |
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| `vpkuhum128` | `vpkuhum128` | — | Vector128 Pack Unsigned Half Word Unsigned Modulo |
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## Syntax
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```asm
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vpkuhum [VD], [VA], [VB]
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vpkuhum128 [VD], [VA], [VB]
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```
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## Encoding
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### `vpkuhum` — form `VX`
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- **Opcode word:** `0x1000000e`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `14`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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### `vpkuhum128` — form `VX128`
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- **Opcode word:** `0x14000300`
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- **Primary opcode (bits 0–5):** `5`
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- **Extended opcode:** `768`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4 or 5) |
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| 6–10 | `VD128l` | destination low 5 bits |
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| 11–15 | `VA128l` | source A low 5 bits |
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| 16–20 | `VB128l` | source B low 5 bits |
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| 21 | `VA128H` | source A high bit |
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| 22 | `—` | reserved |
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| 23–25 | `VC` | optional VC / XO sub-field |
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| 26 | `VA128h` | source A middle bit |
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| 27 | `—` | reserved |
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| 28–29 | `VD128h` | destination high 2 bits |
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| 30–31 | `VB128h` | source B high 2 bits |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vpkuhum: read; vpkuhum128: read | Source A vector register. |
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| `VB` | vpkuhum: read; vpkuhum128: read | Source B vector register. |
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| `VD` | vpkuhum: write; vpkuhum128: write | Destination vector register. |
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## Register Effects
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### `vpkuhum`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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### `vpkuhum128`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vpkuhum`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkuhum"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1909`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1909)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:115`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L115)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:440`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L440)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4019-4030`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4019-L4030)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vpkuhum | PpcOpcode::vpkuhum128 => {
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let is_128 = matches!(instr.opcode, PpcOpcode::vpkuhum128);
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let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
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else { (instr.ra(), instr.rb(), instr.rd()) };
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let a = ctx.vr[ra].as_u16x8();
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let b = ctx.vr[rb].as_u16x8();
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let mut r = [0u8; 16];
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for i in 0..8 { r[i] = a[i] as u8; }
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for i in 0..8 { r[8 + i] = b[i] as u8; }
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ctx.vr[rd] = xenia_types::Vec128::from_bytes(r);
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ctx.pc += 4;
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}
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```
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</details>
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**`vpkuhum128`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkuhum128"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1912`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1912)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:115`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L115)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:626`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L626)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4019-4030`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4019-L4030)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vpkuhum | PpcOpcode::vpkuhum128 => {
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let is_128 = matches!(instr.opcode, PpcOpcode::vpkuhum128);
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let (ra, rb, rd) = if is_128 { (instr.va128(), instr.vb128(), instr.vd128()) }
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else { (instr.ra(), instr.rb(), instr.rd()) };
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let a = ctx.vr[ra].as_u16x8();
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let b = ctx.vr[rb].as_u16x8();
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let mut r = [0u8; 16];
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for i in 0..8 { r[i] = a[i] as u8; }
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for i in 0..8 { r[8 + i] = b[i] as u8; }
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ctx.vr[rd] = xenia_types::Vec128::from_bytes(r);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Unsigned half-word → byte modulo pack.** Each of the 16 input half-word lanes (8 from `VA`, 8 from `VB`) is truncated to its low 8 bits. No saturation; values above 255 wrap modulo 256.
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- **`VSCR[SAT]` is never touched.** This is the `-m` (modulo) form. For saturation use [`vpkuhus`](vpkuhus.md).
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- **Lane-count doubling.** 16 half-word lanes → 16 byte lanes, `VA`'s 8 half-words into `VD.b[0..7]` and `VB`'s 8 into `VD.b[8..15]`.
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- **Cheap "low-byte extract" primitive.** Often used to repack per-channel results after a half-word arithmetic step. Contrast with shifting + masking.
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- **No `Rc`, no XER.**
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- **VMX128 sibling [`vpkuhum128`](vpkuhum128.md).**
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## Related Instructions
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- [`vpkuhus`](vpkuhus.md) — the saturating sibling.
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- [`vpkuwum`](vpkuwum.md) — word → half-word modulo pack.
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- [`vpkshss`](vpkshss.md), [`vpkshus`](vpkshus.md) — signed half-word packs.
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- [`vupkhub`](vupkhub.md) / [`vupklub`](vupklub.md) (if present) — zero-extending byte → half-word unpacks that reverse this op.
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- [`vperm`](vperm.md) — general-purpose alternative when the packing pattern is irregular.
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## IBM Reference
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- [AIX 7.3 — `vpkuhum` (Vector Pack Unsigned Half Word Unsigned Modulo)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vpkuhum-vector-pack-unsigned-half-word-unsigned-modulo-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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