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chore: add migration/ bundle for cross-machine setup

Browse Source 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
commit e6d43a23ac
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# `vsldoi` — Vector Shift Left Double by Octet Immediate
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x1000002c`
<!-- GENERATED: BEGIN -->
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vsldoi` | `vsldoi` | — | Vector Shift Left Double by Octet Immediate |
| `vsldoi128` | `vsldoi128` | — | Vector128 Shift Left Double by Octet Immediate |
## Syntax
```asm
vsldoi [VD], [VA], [VB], [SHB]
vsldoi128 [VD], [VA], [VB], [SHB]
```
## Encoding
### `vsldoi` — form `VA`
- **Opcode word:** `0x1000002c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `44`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |
### `vsldoi128` — form `VX128_5`
- **Opcode word:** `0x10000010`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `16`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22–25 | `SH` | 4-bit shift amount |
| 26 | `VA128h` | source A middle bit |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vsldoi: read; vsldoi128: read | Source A vector register. |
| `VB` | vsldoi: read; vsldoi128: read | Source B vector register. |
| `SHB` | vsldoi: read; vsldoi128: read | Shift amount (byte granularity, `vsldoi`). |
| `VD` | vsldoi: write; vsldoi128: write | Destination vector register. |
## Register Effects
### `vsldoi`
- **Reads (always):** `VA`, `VB`, `SHB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `vsldoi128`
- **Reads (always):** `VA`, `VB`, `SHB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vsldoi`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsldoi"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1477`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1477)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:122`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L122)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:587`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L587)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2303-2314`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2303-L2314)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vsldoi => {
let a_bytes = ctx.vr[instr.ra()].as_bytes();
let b_bytes = ctx.vr[instr.rb()].as_bytes();
let sh = ((instr.raw >> 6) & 0xF) as usize; // SH field bits 6-9
let mut concat = [0u8; 32];
concat[..16].copy_from_slice(&a_bytes);
concat[16..].copy_from_slice(&b_bytes);
let mut r = [0u8; 16];
r.copy_from_slice(&concat[sh..sh + 16]);
ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(r);
ctx.pc += 4;
}
```
</details>
**`vsldoi128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsldoi128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1480`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1480)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:122`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L122)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:595`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L595)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2315-2327`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2315-L2327)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
```rust
PpcOpcode::vsldoi128 => {
let a_bytes = ctx.vr[instr.va128()].as_bytes();
let b_bytes = ctx.vr[instr.vb128()].as_bytes();
let sh = instr.vx128_5_sh() as usize;
let mut concat = [0u8; 32];
concat[..16].copy_from_slice(&a_bytes);
concat[16..].copy_from_slice(&b_bytes);
let mut r = [0u8; 16];
let sh = sh.min(16);
r.copy_from_slice(&concat[sh..sh + 16]);
ctx.vr[instr.vd128()] = xenia_types::Vec128::from_bytes(r);
ctx.pc += 4;
}
```
</details>
<!-- GENERATED: END -->
## Special Cases & Edge Conditions
- **Static byte-level shift of `VA ‖ VB`.** The 4-bit `SHB` immediate names a byte offset into the 32-byte concatenation `VA ‖ VB`. The destination `VD` is the 16-byte window starting at that offset. Equivalently: `VD = (VA << (8 * SHB)) | (VB >> (8 * (16 − SHB)))`, treating the 32-byte concatenation as a single big-endian value.
- **`SHB = 0` is a register move** from `VA` to `VD`. `SHB = 16` is ill-formed; the field is 4 bits (0..15) so the range is `SHB ∈ 0..=15`.
- **Compile-time shift only.** Unlike `vperm` / `vslo` / `vsro`, the shift is an immediate. When the shift is known at compile time, `vsldoi` is strictly cheaper than an `lvsl` + `vperm` pair.
- **Unaligned-load idiom.** `vsldoi` is the static-offset counterpart to the dynamic `lvsl` + `vperm` pattern. When the misalignment is known, emit `vsldoi vD, vAL, vAH, SHB` after two aligned `lvx` loads.
- **Big-endian byte indexing.** Lane 0 is the MSB.
- **No flags, no VSCR.**
- **VMX128 sibling [`vsldoi128`](vsldoi128.md)** with the wider register file; same 4-bit `SHB` immediate.
## Related Instructions
- [`vslo`](vslo.md), [`vsro`](vsro.md) — byte-level (octet) shifts using a per-register count, dynamic.
- [`vsl`](vsl.md), [`vsr`](vsr.md) — bit-level whole-register shifts.
- [`vperm`](vperm.md) — general-purpose programmable byte permute.
- [`lvsl`](lvsl.md), [`lvsr`](lvsr.md) — dynamic permute-control generators.
- [`vmrghb`](vmrghb.md), [`vmrglb`](vmrglb.md) — byte-granularity merges.
## IBM Reference
- [AIX 7.3 — `vsldoi` (Vector Shift Left Double by Octet Immediate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsldoi-vector-shift-left-double-by-octet-immediate-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)