chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
132
migration/project-root/ppc-manual/vmx/vsubsws.md
Normal file
132
migration/project-root/ppc-manual/vmx/vsubsws.md
Normal file
@@ -0,0 +1,132 @@
|
||||
# `vsubsws` — Vector Subtract Signed Word Saturate
|
||||
|
||||
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000780`
|
||||
|
||||
<!-- GENERATED: BEGIN -->
|
||||
|
||||
## Assembler Mnemonics
|
||||
|
||||
| Mnemonic | XML entry | Flags | Description |
|
||||
| --- | --- | --- | --- |
|
||||
| `vsubsws` | `vsubsws` | — | Vector Subtract Signed Word Saturate |
|
||||
|
||||
## Syntax
|
||||
|
||||
```asm
|
||||
vsubsws [VD], [VA], [VB]
|
||||
```
|
||||
|
||||
## Encoding
|
||||
|
||||
### `vsubsws` — form `VX`
|
||||
|
||||
- **Opcode word:** `0x10000780`
|
||||
- **Primary opcode (bits 0–5):** `4`
|
||||
- **Extended opcode:** `1920`
|
||||
- **Synchronising:** no
|
||||
|
||||
| Bits | Field | Meaning |
|
||||
| --- | --- | --- |
|
||||
| 0–5 | `OPCD` | primary opcode (4) |
|
||||
| 6–10 | `VRT/VD` | destination vector register |
|
||||
| 11–15 | `VRA/VA` | source A vector register |
|
||||
| 16–20 | `VRB/VB` | source B vector register |
|
||||
| 21–31 | `XO` | extended opcode (11 bits) |
|
||||
|
||||
## Operands
|
||||
|
||||
| Field | Role | Description |
|
||||
| --- | --- | --- |
|
||||
| `VA` | vsubsws: read | Source A vector register. |
|
||||
| `VB` | vsubsws: read | Source B vector register. |
|
||||
| `VD` | vsubsws: write | Destination vector register. |
|
||||
| `VSCR` | vsubsws: write | Vector Status and Control Register (NJ/SAT bits). |
|
||||
|
||||
## Register Effects
|
||||
|
||||
### `vsubsws`
|
||||
|
||||
- **Reads (always):** `VA`, `VB`
|
||||
- **Reads (conditional):** _none_
|
||||
- **Writes (always):** `VD`, `VSCR`
|
||||
- **Writes (conditional):** _none_
|
||||
|
||||
## Status-Register Effects
|
||||
|
||||
- `vsubsws`: **VSCR[SAT]** may be stickied on saturating vector operations.
|
||||
|
||||
## Operation (pseudocode)
|
||||
|
||||
```
|
||||
; Pseudocode derives directly from the xenia-rs interpreter
|
||||
; arm (see Implementation References). Operation semantics:
|
||||
; - Read source operands from the fields listed under Operands.
|
||||
; - Apply the arithmetic / logical / memory action described
|
||||
; in the Description field above.
|
||||
; - Write results to the destination register(s); update any
|
||||
; status bits enumerated under Status-Register Effects.
|
||||
; Consult the IBM AIX reference link under IBM Reference for
|
||||
; canonical PPC-style pseudocode where xenia's expression is
|
||||
; terse.
|
||||
```
|
||||
|
||||
## C Translation Example
|
||||
|
||||
```c
|
||||
/* C translation: the xenia-rs interpreter arm below in */
|
||||
/* Implementation References is the authoritative semantic */
|
||||
/* snapshot. Translate it line-by-line: */
|
||||
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
|
||||
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
|
||||
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
|
||||
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
|
||||
/* The Register Effects and Status-Register Effects tables above */
|
||||
/* enumerate every side effect a faithful translation must emit. */
|
||||
```
|
||||
|
||||
## Implementation References
|
||||
|
||||
**`vsubsws`**
|
||||
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsubsws"`](../../xenia-canary/tools/ppc-instructions.xml)
|
||||
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1711`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1711)
|
||||
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:125`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L125)
|
||||
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:549`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L549)
|
||||
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3366-3377`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3366-L3377)
|
||||
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
|
||||
|
||||
```rust
|
||||
PpcOpcode::vsubsws => {
|
||||
let a = crate::vmx::as_i32x4(ctx.vr[instr.ra()]);
|
||||
let b = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
|
||||
let mut r = [0i32; 4]; let mut sat = false;
|
||||
for i in 0..4 {
|
||||
let (v, s) = crate::vmx::sat_sub_i32(a[i], b[i]);
|
||||
r[i] = v; sat |= s;
|
||||
}
|
||||
if sat { ctx.set_vscr_sat(true); }
|
||||
ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
|
||||
ctx.pc += 4;
|
||||
}
|
||||
```
|
||||
</details>
|
||||
|
||||
<!-- GENERATED: END -->
|
||||
|
||||
## Special Cases & Edge Conditions
|
||||
|
||||
- **Signed word saturating subtract.** `VD.w[i] = clamp_int32(VA.w[i] − VB.w[i])` for 4 lanes. Overflow clamps to `±0x7FFFFFFF` and sticky-sets `VSCR[SAT]`. Xenia uses `vmx::sat_sub_i32`.
|
||||
- **Sticky VSCR[SAT].**
|
||||
- **Big-endian word lanes.**
|
||||
- **No `Rc`, no XER.**
|
||||
- **No VMX128 sibling.**
|
||||
|
||||
## Related Instructions
|
||||
|
||||
- [`vaddsws`](vaddsws.md) — signed word saturating add.
|
||||
- [`vsubuws`](vsubuws.md), [`vsubuwm`](vsubuwm.md) — unsigned word sub (sat / mod).
|
||||
- [`vsubsbs`](vsubsbs.md), [`vsubshs`](vsubshs.md) — byte / half-word signed saturating subs.
|
||||
|
||||
## IBM Reference
|
||||
|
||||
- [AIX 7.3 — `vsubsws` (Vector Subtract Signed Word Saturate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsubsws-vector-subtract-signed-word-saturate-instruction)
|
||||
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
|
||||
Reference in New Issue
Block a user