chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/vmx/vsum2sws.md
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migration/project-root/ppc-manual/vmx/vsum2sws.md
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# `vsum2sws` — Vector Sum Across Partial (1/2) Signed Word Saturate
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> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000688`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `vsum2sws` | `vsum2sws` | — | Vector Sum Across Partial (1/2) Signed Word Saturate |
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## Syntax
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```asm
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vsum2sws [VD], [VA], [VB]
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```
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## Encoding
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### `vsum2sws` — form `VX`
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- **Opcode word:** `0x10000688`
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- **Primary opcode (bits 0–5):** `4`
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- **Extended opcode:** `1672`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (4) |
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| 6–10 | `VRT/VD` | destination vector register |
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| 11–15 | `VRA/VA` | source A vector register |
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| 16–20 | `VRB/VB` | source B vector register |
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| 21–31 | `XO` | extended opcode (11 bits) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `VA` | vsum2sws: read | Source A vector register. |
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| `VB` | vsum2sws: read | Source B vector register. |
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| `VD` | vsum2sws: write | Destination vector register. |
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| `VSCR` | vsum2sws: write | Vector Status and Control Register (NJ/SAT bits). |
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## Register Effects
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### `vsum2sws`
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- **Reads (always):** `VA`, `VB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `VD`, `VSCR`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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- `vsum2sws`: **VSCR[SAT]** may be stickied on saturating vector operations.
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`vsum2sws`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsum2sws"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1776`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1776)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:127`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L127)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:545`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L545)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3668-3679`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3668-L3679)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::vsum2sws => {
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// Two 2-word partial sums at lanes 1 and 3.
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let a = crate::vmx::as_i32x4(ctx.vr[instr.ra()]);
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let c = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
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let s0 = a[0] as i64 + a[1] as i64 + c[1] as i64;
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let s1 = a[2] as i64 + a[3] as i64 + c[3] as i64;
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let (v0, sat0) = crate::vmx::sat_i64_to_i32(s0);
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let (v1, sat1) = crate::vmx::sat_i64_to_i32(s1);
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if sat0 | sat1 { ctx.set_vscr_sat(true); }
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ctx.vr[instr.rd()] = crate::vmx::from_i32x4([0, v0, 0, v1]);
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Two 2-word partial sums.** The four signed-word lanes of `VA` are split into two pairs: `{VA.w[0], VA.w[1]}` and `{VA.w[2], VA.w[3]}`. Each pair is summed, then added to the matching "anchor" word of `VB` (`VB.w[1]` and `VB.w[3]` respectively). Each 33-bit intermediate result is saturated to `int32`.
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- **Output lane placement.** `VD.w[0] = 0`, `VD.w[1] = sat(VA.w[0] + VA.w[1] + VB.w[1])`, `VD.w[2] = 0`, `VD.w[3] = sat(VA.w[2] + VA.w[3] + VB.w[3])`. The zero lanes are specified in the ISA — software that wants a contiguous pair must `vmrglw` / `vmrghw` afterwards.
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- **Sticky VSCR[SAT]** set when either saturating truncation occurs.
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- **Big-endian word lanes.**
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- **No `Rc`, no XER.**
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- **No VMX128 sibling.**
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## Related Instructions
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- [`vsumsws`](vsumsws.md) — full 4-lane sum.
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- [`vsum4sbs`](vsum4sbs.md), [`vsum4shs`](vsum4shs.md), [`vsum4ubs`](vsum4ubs.md) — per-word partial sums at narrower input widths.
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- [`vaddsws`](vaddsws.md), [`vsubsws`](vsubsws.md) — word-saturating arithmetic.
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## IBM Reference
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- [AIX 7.3 — `vsum2sws` (Vector Sum across Partial (1/2) Saturated Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsum2sws-vector-sum-across-partial-12-saturated-word-instruction)
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- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)
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