xenia-memory: interior-mutable writes, page versioning, fenced ops

Re-shape MemoryAccess so write methods take &self and rely on interior
mutability (atomics in GuestMemory, Cell in test mocks). This unblocks
the &Arc<KernelState>-only execution model the CPU/HLE crates moved to.

GuestMemory grows: per-4 KiB-page write-version counter (page_version)
that the CPU's decode cache and the texture cache observe via Acquire,
fenced 32-bit/64-bit read/write helpers (Release on writer / Acquire on
reader) that PM4_EVENT_WRITE_SHD and the matching CPU consumers use to
synchronize fence publication, and broader page-table / heap accounting
needed by the new HLE allocators.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

crates/xenia-memory/src/page_table.rs

@@ -6,6 +6,19 @@ use bitflags::bitflags;
 pub struct PageEntry(u64);
 
 impl PageEntry {
+    /// Reconstruct a [`PageEntry`] from its packed `u64` representation.
+    /// Used by [`crate::GuestMemory::is_mapped`] and `page_entry` after an
+    /// atomic load from the page table.
+    pub fn from_raw(raw: u64) -> Self {
+        Self(raw)
+    }
+
+    /// The packed `u64` representation, ready to atomically Release-store
+    /// into the page table.
+    pub fn raw(&self) -> u64 {
+        self.0
+    }
+
     /// Base address of the allocated region in 4K pages (20 bits).
     pub fn base_address(&self) -> u32 {
         (self.0 & 0xFFFFF) as u32