2 Commits

Author	SHA1	Message	Date
MechaCat02	2f55d1fd7d	[iterate-2X] Texture pipeline: un-stub RectangleList + draw-time texture decode ... Two faithful, deterministic GPU-backend changes that make the texture path correct for whatever textured draw the splash eventually dispatches. Both are currently inert on Sylpheed (the textured logo draw is still gated downstream — see below), but neither shifts the stable-digest golden, so they land safely. 1. Un-stub RectangleList primitive expansion (primitive.rs). The splash submits 2819 RectangleList draws at 200M, all of which were REJECTED by the P3 stub (`gpu.primitive.rejected{rectangle_list}`) → only ~592 flat point/quad draws rasterized. Mirror canary's intent (primitive_processor.cc:389-456 kRectangleListAsTriangleStrip) within our CPU index-rewrite idiom: emit each rect's 3 real vertices as one TriangleList triangle (v0,v1,v2), rejected=false, faithful host_vertex_count. The full quad (synthesized 4th corner v3=v0+v2-v1) needs real vertex fetch in vs_main — left as a documented TODO. Rejection warnings drop 2819→0. 2. Draw-time texture decode keyed off the active PS's real tfetch slots (gpu_system.rs + exports.rs vd_swap). Previously vd_swap decoded a hardcoded fetch-constant slot 0 at swap time. Now the DRAW handler parses the bound pixel shader (ucode::parse_shader), collects its tfetch fetch_const slots via new shader_metrics::tfetch_slots, reads each 6-dword fetch constant, and decode+caches it into GpuSystem::last_draw_textures. vd_swap publishes the first of these (UI binds one texture today), falling back to the legacy slot-0 probe on flat-only frames. New span_max_version helper walks page_version over the trait (draw-time &dyn MemoryAccess lacks the heap's inherent max_page_version). Pure function of guest writes — deterministic. Status: texture_decodes stays 0 on Sylpheed because all 6 live shaders are flat (no tfetch); canary's textured logo shaders E59B2B3D/F7B1457 are not yet dispatched by ours (a downstream title-state gate, the next frontier). The full P5 decode→publish→upload→sample path is already wired; this makes the decode side key off the real shader instead of a guess. Validation: stable-digest golden sylpheed_n50m unchanged (draws=718 swaps=147 tex=0), regenerated twice byte-identical; 200M run shows 0 RectangleList rejections. cargo test --workspace green (677, +2: rectangle_list_expansion, tfetch_slots_extracts_texture_fetch_constants). No temp hooks. Branch only; not pushed/merged. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>	2026-06-14 21:34:43 +02:00
MechaCat02	79eb52c378	xenia-gpu: end-to-end Xenos pipeline (PM4, ucode, EDRAM, resolve) ... First real GPU implementation. Ring/PM4 frontend (ring_view, ring_drain, pm4) drains the command processor; gpu_system owns the threaded backend (DrainFence RPC + parker/fence helpers from M1) and the MMIO-mapped register block (mmio_region). Xenos shader frontend: ucode/{alu,control_flow,fetch,mod}.rs decode the Xbox 360 microcode, translator.rs lowers it onto the WGSL xenos_interp interpreter shader (shaders/xenos_interp.wgsl). shader_metrics.rs counts decode/translate work. Render state: draw_state, primitive, render_target_cache, texture_cache, tiled_address (Xenos's swizzled tiled-memory layout), xenos_constants (register field constants), edram (the 10 MiB EDRAM model with MSAA), and resolve.rs (TILE_FLUSH copy-out — clear-resolve plus bitwise-equivalent 32 bpp + 64 bpp paths landed). handle.rs owns the typed GPU-resource handles the kernel hands out. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>	2026-05-01 16:29:38 +02:00