# `cmp` — Compare > **Category:** [Integer ALU](../categories/alu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c000000` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `cmp` | `cmp` | — | Compare | ## Syntax ```asm cmp [CRFD], [L], [RA], [RB] ``` ## Encoding ### `cmp` — form `X` - **Opcode word:** `0x7c000000` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `0` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ## Operands | Field | Role | Description | | --- | --- | --- | | `L` | cmp: read | Operand-length bit for compare instructions (`0 ⇒ 32-bit`, `1 ⇒ 64-bit`). | | `RA` | cmp: read | Source GPR (`r0`–`r31`). | | `RB` | cmp: read | Source GPR. | | `CRFD` | cmp: write | CR destination field (`crf`, 0–7). | ## Register Effects ### `cmp` - **Reads (always):** `L`, `RA`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** `CRFD` - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` if L = 0 then a,b <- EXTS((RA)[32:63]), EXTS((RB)[32:63]) else a,b <- (RA), (RB) CR[BF] <- signed_compare(a, b) || XER[SO] ``` ## C Translation Example ```c /* C translation: the xenia-rs interpreter arm below in */ /* Implementation References is the authoritative semantic */ /* snapshot. Translate it line-by-line: */ /* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */ /* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */ /* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */ /* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`cmp`** - xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="cmp"`](../../xenia-canary/tools/ppc-instructions.xml) - xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:523`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L523) - xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:13`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L13) - xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:749`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L749) - xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:863-885`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L863-L885)
xenia-rs interpreter body (frozen snapshot) ```rust PpcOpcode::cmp => { let bf = instr.crfd(); if instr.l() { let ra = ctx.gpr[instr.ra()] as i64; let rb = ctx.gpr[instr.rb()] as i64; ctx.cr[bf] = crate::context::CrField { lt: ra < rb, gt: ra > rb, eq: ra == rb, so: ctx.xer_so != 0, }; } else { let ra = ctx.gpr[instr.ra()] as i32; let rb = ctx.gpr[instr.rb()] as i32; ctx.cr[bf] = crate::context::CrField { lt: ra < rb, gt: ra > rb, eq: ra == rb, so: ctx.xer_so != 0, }; } ctx.pc += 4; } ```
## Extended Pseudocode ``` if L = 0 then ; 32-bit compare a <- EXTS((RA)[32:63]) ; sign-extend low word to 64 b <- EXTS((RB)[32:63]) else ; 64-bit compare a <- (RA) b <- (RB) CR[BF] <- { LT: a s b, EQ: a = b, SO: XER[SO] } ; signed ``` ## Special Cases & Edge Conditions - **`BF` is a CR field (0–7), not a bit.** The `crfD` operand encodes which of the eight 4-bit CR fields is updated. Assemblers write it as `crN` where `N ∈ 0..7`. The simplified mnemonic `cmpw RA, RB` ≡ `cmp cr0, 0, RA, RB` is universal in Xbox 360 code. - **`L` bit selects width.** `L = 0` (the usual `cmpw` / `cmpd`-is-rare path) performs a *32-bit* signed compare of `RA[32:63]` and `RB[32:63]`, both sign-extended to 64 bits. `L = 1` (`cmpd`) performs a full 64-bit signed compare. - **Signed.** Use [`cmpl`](cmpl.md) / [`cmpli`](cmpli.md) for unsigned comparisons. Confusing signed/unsigned is the most common compare-family bug in hand-written asm. - **SO is always copied from `XER[SO]`.** This makes overflow observable across arithmetic/compare sequences: an `addo.` followed by `beq` can branch on the record-form flag while `bso` can inspect the sticky overflow. - **`cr0` is the default for record-form ALU**; by convention assemblers and generators reserve `cr0` for the chain of `Rc=1` instructions and use `cr1..cr7` (or `cmp` to an explicit field) for standalone compares. Don't assume `cmp` writes `cr0` unless the `BF` operand says so. - **No register is written** beyond the 4-bit CR field. `cmp` has no `Rc` or `OE` bit. - **Xenia-rs quirk.** The interpreter recomputes `EQ` after the signed compare to guard against a subtract-cancellation edge case; this is a defensive belt-and-braces against the 32-bit narrowing path. Functionally equivalent to the spec. ## Related Instructions - [`cmpi`](cmpi.md) — signed compare against a 16-bit immediate. - [`cmpl`](cmpl.md), [`cmpli`](cmpli.md) — unsigned versions. - [`cmpw`](cmp.md), [`cmpd`](cmp.md) — simplified mnemonics selecting `L`. - [`mcrxr`](mcrxr.md) — move `XER[SO..CA]` into a CR field and clear them; used to reset sticky overflow. - Every `Rc=1` ALU instruction ([`addx`](addx.md), [`subfx`](subfx.md), [`andx`](andx.md), …) — these implicitly perform a signed-compare-to-zero into `cr0`; use explicit `cmp` only when comparing two non-zero values or using a non-zero CR field. ## IBM Reference - [AIX 7.3 — `cmp` (Compare)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-cmp-compare-instruction) - [AIX 7.3 — `cmpw` / `cmpd` (simplified mnemonics)](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-cmpw-compare-word)