# `extswx` — Extend Sign Word

> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0007b4`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `extsw` | `extswx` | — | Extend Sign Word |
| `extsw.` | `extswx` | Rc=1 | Extend Sign Word |

## Syntax

```asm
extsw[Rc] [RA], [RS]
```

## Encoding

### `extswx` — form `X`

- **Opcode word:** `0x7c0007b4`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `986`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RS` | extswx: read | Source GPR (alias for RD in some stores). |
| `RA` | extswx: write | Source GPR (`r0`–`r31`). |
| `CR` | extswx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |

## Register Effects

### `extswx`

- **Reads (always):** `RS`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `extswx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.

## Operation (pseudocode)

```
RA <- EXTS_32_to_64((RS)[32:63])
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`extswx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="extswx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:740`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L740)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:25`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L25)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:852`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L852)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:603-607`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L603-L607)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::extswx => {
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] as i32 as i64 as u64;
            if instr.rc_bit() { ctx.update_cr_signed(0, ctx.gpr[instr.ra()] as i64); }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Sign-extends the low 32 bits of `RS` to 64 bits.** Bit 32 (sign bit of the word) is replicated through bits 0–31 of `RA`.
- **Used heavily in 32-to-64-bit promotion.** Most Xbox 360 ABI parameters are 32-bit; promoting a 32-bit `int` to a 64-bit GPR requires this instruction. Many functions emit it on entry to canonicalise their argument registers.
- **`Rc=1` CR0 update is correctly 64-bit.** [`interpreter.rs:399`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L399) uses `as i64` (no truncation) — one of the few xenia-rs sites where the spec width is honoured. The signed compare in CR0 reflects the full sign-extended value.
- **Operand convention** is the X-form one (`RA` destination, `RS` source).
- **No `XER` side effects.**
- **`RB` field unused.**
- **Aliasing is fine.** `extsw r3, r3` is the canonical "sign-extend in place" idiom.
- **Distinct from `srawi RA, RS, 31`**, which produces the *sign mask* (`-1` if negative else `0`) rather than the sign-extended value.

## Related Instructions

- [`extsbx`](extsbx.md), [`extshx`](extshx.md) — narrower sign extensions.
- [`srawix`](srawix.md) — to derive a sign mask instead.
- [`rldiclx`](rldiclx.md) — to *zero*-extend the low 32 bits.
- `lwa` / `lwax` (memory ops) — combined load-and-sign-extend; lives outside this set.

## IBM Reference

- [AIX 7.3 — `extsw` (Extend Sign Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-extsw-extend-sign-word-instruction)