# `fctiwzx` — Floating Convert to Integer Word with Round Toward Zero

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc00001e`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fctiwz` | `fctiwzx` | — | Floating Convert to Integer Word with Round Toward Zero |
| `fctiwz.` | `fctiwzx` | Rc=1 | Floating Convert to Integer Word with Round Toward Zero |

## Syntax

```asm
fctiwz[Rc] [FD], [FB]
```

## Encoding

### `fctiwzx` — form `X`

- **Opcode word:** `0xfc00001e`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `15`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FB` | fctiwzx: read | Source B floating-point register. |
| `FD` | fctiwzx: write | Destination floating-point register. |
| `CR` | fctiwzx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | fctiwzx: write | Floating-Point Status and Control Register. |

## Register Effects

### `fctiwzx`

- **Reads (always):** `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `fctiwzx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fctiwzx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fctiwzx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:313`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L313)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:27`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L27)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:900`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L900)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2949-2969`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2949-L2969)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::fctiwzx => {
            // Convert to integer word (round toward zero).
            // PPCBUG-230: set XX on inexact.
            let val = ctx.fpr[instr.rb()];
            let result_u32: u32 = if val.is_nan() {
                fpscr::set_exception(ctx, fpscr::VXCVI | if fpscr::is_snan(val) { fpscr::VXSNAN } else { 0 });
                0x8000_0000
            } else if val > (i32::MAX as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x7FFF_FFFF
            } else if val < (i32::MIN as f64) {
                fpscr::set_exception(ctx, fpscr::VXCVI);
                0x8000_0000
            } else {
                if val != val.trunc() { fpscr::set_exception(ctx, fpscr::XX); }
                val.trunc() as i32 as u32
            };
            ctx.fpr[instr.rd()] = f64::from_bits(result_u32 as u64);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **binary64 → 32-bit signed integer, round toward zero.** Truncates regardless of `FPSCR[RN]`. xenia-rs uses `clamp` to saturate to `[i32::MIN, i32::MAX]` then `as i32`, which truncates — matching PPC `fctiwz` semantics.
- **Most common conversion in compiled code.** Translates C/C++ `(int32_t)f` casts, which require truncation per the C standard.
- **Saturation on out-of-range.** Hardware saturates to `i32::MAX` for large positives, `i32::MIN` for large negatives or NaN, and sets `FPSCR[VXCVI, VX, FX]`. xenia's explicit `clamp` correctly reproduces the saturation, but does not raise FPSCR bits (xenia quirk).
- **NaN sentinel.** xenia returns `0x0000_0000_8000_0000` (i.e. `i32::MIN` in low 32 bits). Matches PPC sentinel.
- **High 32 bits of FPR.** Architecturally undefined per PowerISA, but xenia produces zero-extended `u32`. Use `stfiwx` (store low 32 bits) — never `stfd` — for the canonical "store this integer" idiom.
- **Inexact.** Sets `FPSCR[XX, FX]` on any non-integer input. xenia does not update FPSCR.
- **`Rc=1` (`fctiwz.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **Encoding.** X-form, primary 63, XO 15. Reads `FRB` only.

## Related Instructions

- [`fctiwx`](fctiwx.md) — 32-bit integer with `FPSCR[RN]` rounding.
- [`fctidx`](fctidx.md), [`fctidzx`](fctidzx.md) — 64-bit integer variants.
- [`fcfidx`](fcfidx.md) — inverse direction (i64 → f64); for i32 → f64, sign-extend to i64 first.
- `stfiwx` — store low 32 bits of FPR; canonical companion.
- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — FPSCR control (no effect on `fctiwz` since rounding mode is fixed to truncation).

## IBM Reference

- [AIX 7.3 — `fctiwz` (Floating Convert to Integer Word with Round Toward Zero)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fctiwz-floating-convert-integer-word-round-toward-zero-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/).