# `fnmaddx` — Floating Negative Multiply-Add

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xfc00003e`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fnmadd` | `fnmaddx` | — | Floating Negative Multiply-Add |
| `fnmadd.` | `fnmaddx` | Rc=1 | Floating Negative Multiply-Add |

## Syntax

```asm
fnmadd[Rc] [FD], [FA], [FC], [FB]
```

## Encoding

### `fnmaddx` — form `A`

- **Opcode word:** `0xfc00003e`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `31`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (59 or 63) |
| 6–10 | `FRT` | destination FPR |
| 11–15 | `FRA` | source A FPR |
| 16–20 | `FRB` | source B FPR |
| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
| 26–30 | `XO` | extended opcode (5 bits) |
| 31 | `Rc` | record-form flag (updates CR1) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FA` | fnmaddx: read | Source A floating-point register (`fr0`–`fr31`). |
| `FC` | fnmaddx: read | Source C floating-point register (for madd-style ops). |
| `FB` | fnmaddx: read | Source B floating-point register. |
| `FD` | fnmaddx: write | Destination floating-point register. |
| `CR` | fnmaddx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | fnmaddx: write | Floating-Point Status and Control Register. |

## Register Effects

### `fnmaddx`

- **Reads (always):** `FA`, `FC`, `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `fnmaddx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
FRT <- −((FRA × FRC) + FRB)
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fnmaddx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fnmaddx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:213`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L213)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:29`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L29)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:930`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L930)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2692-2705`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2692-L2705)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::fnmaddx => {
            // PPCBUG-203: missing VXISI. PPCBUG-205: NaN sign preserved (no negation on NaN).
            let a = ctx.fpr[instr.ra()];
            let c = ctx.fpr[instr.rc()];
            let b = ctx.fpr[instr.rb()];
            fpscr::check_invalid_mul(ctx, a, c);
            fpscr::check_invalid_fma_add(ctx, a, c, b, false);
            let fma = a.mul_add(c, b);
            let result = if fma.is_nan() { fma } else { -fma };
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite() && c.is_finite());
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Single rounding step, then sign flip.** Computes `−((FRA × FRC) + FRB)` with one fused rounding for the FMA; the final negation is a bit-pattern sign-flip and does not introduce additional rounding error. xenia-rs implements this as `-(a.mul_add(c, b))`.
- **Sign of NaN.** Per PowerISA, `fnmadd` does **not** flip the sign of a NaN result. xenia uses Rust's `Neg` which does flip the NaN sign bit (`f64::neg`); for IEEE-754 binary64 this is observable through bit-level inspection but not through arithmetic comparisons. **xenia quirk** — title code that inspects NaN sign bits will diverge.
- **Operand order.** Assembler: `FD, FA, FC, FB`.
- **Invalid operations.** Same as `fmadd`: `VXIMZ` for `0×∞`, `VXISI` for opposing-infinity collision. Quiet NaN result.
- **FPSCR side effects.** Hardware updates `FPRF`, `FR`, `FI`, `FX`, `OX`, `UX`, `XX`, `VXIMZ`, `VXISI`, `VXSNAN`. xenia-rs does not (xenia quirk).
- **`Rc=1` (`fnmadd.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **NaN propagation.** Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
- **Use case.** Computing `-a*c - b` directly without an intermediate negate. Useful in iterative solvers and in transforming polynomial coefficients.
- **Denormal flush.** Xenon boots with `FPSCR[NI]=1`; xenia uses host IEEE behavior.

## Related Instructions

- [`fnmaddsx`](fnmaddsx.md) — single-precision sibling.
- [`fmaddx`](fmaddx.md), [`fmsubx`](fmsubx.md), [`fnmsubx`](fnmsubx.md) — other fused multiply-add variants:
  - `fmadd` = `(A×C) + B`
  - `fmsub` = `(A×C) − B`
  - `fnmsub` = `−((A×C) − B)`
- [`fnegx`](fnegx.md), [`fnabsx`](fnabsx.md) — sign-bit operations on FPRs.
- [`fmulx`](fmulx.md), [`faddx`](faddx.md) — non-fused decomposition.

## IBM Reference

- [AIX 7.3 — `fnmadd` (Floating Negative Multiply-Add)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fnma-fnmadd-floating-negative-multiply-add-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (note: PowerISA specifies the negation does not flip NaN sign bits).