# `frsqrtex` — Floating Reciprocal Square Root Estimate

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xfc000034`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `frsqrte` | `frsqrtex` | — | Floating Reciprocal Square Root Estimate |
| `frsqrte.` | `frsqrtex` | Rc=1 | Floating Reciprocal Square Root Estimate |

## Syntax

```asm
frsqrte[Rc] [FD], [FB]
```

## Encoding

### `frsqrtex` — form `A`

- **Opcode word:** `0xfc000034`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `26`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (59 or 63) |
| 6–10 | `FRT` | destination FPR |
| 11–15 | `FRA` | source A FPR |
| 16–20 | `FRB` | source B FPR |
| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
| 26–30 | `XO` | extended opcode (5 bits) |
| 31 | `Rc` | record-form flag (updates CR1) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FB` | frsqrtex: read | Source B floating-point register. |
| `FD` | frsqrtex: write | Destination floating-point register. |
| `CR` | frsqrtex: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | frsqrtex: write | Floating-Point Status and Control Register. |

## Register Effects

### `frsqrtex`

- **Reads (always):** `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `frsqrtex`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`frsqrtex`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="frsqrtex"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:118`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L118)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:29`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L29)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:926`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L926)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2836-2853`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2836-L2853)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::frsqrtex => {
            // Reciprocal square root estimate: frD = 1.0 / sqrt(frB)
            let b = ctx.fpr[instr.rb()];
            if b == 0.0 {
                fpscr::set_exception(ctx, fpscr::ZX);
            }
            if b.is_sign_negative() && b != 0.0 && !b.is_nan() {
                fpscr::set_exception(ctx, fpscr::VXSQRT);
            }
            if fpscr::is_snan(b) {
                fpscr::set_exception(ctx, fpscr::VXSNAN);
            }
            let result = 1.0 / b.sqrt();
            ctx.fpr[instr.rd()] = result;
            fpscr::update_after_op(ctx, result, b.is_finite() && b > 0.0);
            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Reciprocal-square-root estimate.** PowerISA: low-precision approximation of `1/sqrt(FRB)` accurate to roughly 12–14 bits, designed as the seed for Newton-Raphson refinement. **xenia quirk:** xenia-rs computes the *full-precision* `1.0 / b.sqrt()` (no rounding to single — `frsqrte` is double-precision per the spec). The result is far more accurate than hardware. Title code that depends on the limited precision still functions; the NR refinement converges in one iteration on either platform.
- **Double precision result.** Per PowerISA, `frsqrte` returns a binary64 estimate (not a single-rounded value, unlike `fres`).
- **Negative input is invalid.** `frsqrte(x < 0)` (other than `-0`) sets `FPSCR[VXSQRT, VX, FX]` and yields a quiet NaN. xenia returns host NaN (Rust's `f64::sqrt` of a negative is NaN, then `1/NaN` is NaN) but does not raise the FPSCR bit.
- **`frsqrte(+0) = +∞`** and sets `FPSCR[ZX]` per spec. **`frsqrte(-0) = -∞`**.
- **`frsqrte(+∞) = +0`**.
- **NaN propagation.** Quiet NaN; signalling NaNs are quietened.
- **`Rc=1` (`frsqrte.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **Encoding.** A-form, primary 63, XO 26. Reads `FRB` only; `FRA`/`FRC` are don't-care.
- **Use case.** The canonical `length`/`normalize` recipe: `inv_len = frsqrte(dot); inv_len = 0.5 * inv_len * (3 - dot * inv_len * inv_len);` — one NR step gets to full double precision. For single precision use `frsp` after.
- **Performance.** Cheap on Xenon. The `length`/`normalize` macro built on `frsqrte` is the hot inner loop in any 3D Xbox 360 game.

## Related Instructions

- [`fresx`](fresx.md) — reciprocal estimate; same NR-refinement design pattern.
- [`fsqrtx`](fsqrtx.md), [`fsqrtsx`](fsqrtsx.md) — full-precision square root (multi-cycle, non-pipelined).
- [`fmulx`](fmulx.md), [`fmaddx`](fmaddx.md), [`fnmsubx`](fnmsubx.md) — the multiply/FMA ops that drive NR refinement.
- [`frspx`](frspx.md) — round to single after `frsqrte` for graphics-pipeline producers expecting `float`.

## IBM Reference

- [AIX 7.3 — `frsqrte` (Floating Reciprocal Square Root Estimate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-frsqrte-floating-reciprocal-square-root-estimate-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (relative-error bound for `frsqrte`; canonical NR refinement step).