# `lvlx` — Load Vector Left Indexed

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00040e`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `lvlx` | `lvlx` | — | Load Vector Left Indexed |
| `lvlx128` | `lvlx128` | — | Load Vector Left Indexed 128 |

## Syntax

```asm
lvlx [VD], [RA0], [RB]
lvlx128 [VD], [RA0], [RB]
```

## Encoding

### `lvlx` — form `X`

- **Opcode word:** `0x7c00040e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `519`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

### `lvlx128` — form `VX128_1`

- **Opcode word:** `0x10000403`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `1027`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA0` | lvlx: read; lvlx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | lvlx: read; lvlx128: read | Source GPR. |
| `VD` | lvlx: write; lvlx128: write | Destination vector register. |

## Register Effects

### `lvlx`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

### `lvlx128`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`lvlx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvlx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:216`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L216)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:44`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L44)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:815`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L815)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3083-3087`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3083-L3087)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::lvlx | PpcOpcode::lvlxl => {
            let ea = ea_indexed(ctx, instr);
            ctx.vr[instr.rd()] = crate::vmx::load_vector_left(mem, ea);
            ctx.pc += 4;
        }
```
</details>

**`lvlx128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvlx128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:219`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L219)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:44`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L44)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:420`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L420)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3088-3092`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3088-L3092)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::lvlx128 | PpcOpcode::lvlxl128 => {
            let ea = ea_indexed(ctx, instr);
            ctx.vr[instr.vd128()] = crate::vmx::load_vector_left(mem, ea);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Load-left half of an unaligned vector.** `lvlx` reads `(16 - (EA mod 16))` bytes starting at the **exact** `EA` and places them in the **left** (high-address-byte → low-lane) of the destination vector; the remaining lanes on the right are zero-filled. Combine with `lvrx` at `EA + 15` to assemble a full unaligned vector across an alignment boundary.
- **Companion idiom.** `lvlx VD, RA, RB ; lvrx Vtemp, RA, RB ; vor VD, VD, Vtemp` produces the unaligned 16 bytes at `EA` regardless of alignment. This was the canonical unaligned-vector-read recipe before `lvsl`/`vperm` shuffles became the more common idiom.
- **No alignment masking.** Unlike `lvx`, the EA is **not** rounded down. `EA mod 16` controls how the data is shifted into the destination.
- **`RA0` semantics.** `RA = 0` selects literal zero.
- **Microsoft Xbox 360 specific.** `lvlx` and `lvrx` are not in the standard Altivec specification — they are part of Microsoft's VMX128 / Cell BE-style extension, defined in PowerPC Cell and later VMX. The Xbox 360 Xenon supports them (decoder + xenia entry confirm).
- **Implementation in xenia.** The shared snapshot calls `vmx::load_vector_left(mem, ea)`, which performs the unaligned partial-byte read and zero-fills the right side.
- **VMX128 sibling (`lvlx128`).** Same semantics; different operand encoding (7-bit register field, addressing `v0..v127`).
- **`lvlxl` is the LRU-hint variant.** Same data behaviour, hint ignored under emulation.

## Related Instructions

- [`lvrx`](lvrx.md), [`lvrx128`](lvrx.md) — load-right partner; combine to read unaligned 16 bytes.
- [`lvlxl`](lvlxl.md), [`lvlxl128`](lvlxl.md) — LRU-hint variants.
- [`lvx`](lvx.md), [`lvx128`](lvx.md) — aligned load (the EA-masking sibling).
- [`stvlx`](stvlx.md), [`stvrx`](stvrx.md) — symmetric unaligned stores.

## IBM Reference

- [AIX 7.3 — `lvlx` (Load Vector Left Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lvlx-load-vector-left-indexed-instruction)
- `PowerISA v2.07B Book I` "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 details.