# `std` — Store Doubleword
> **Category:** [Memory](../categories/memory.md) · **Form:** [DS](../forms/DS.md) · **Opcode:** `0xf8000000`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `std` | `std` | — | Store Doubleword |
| `stdu` | `stdu` | — | Store Doubleword with Update |
| `stdux` | `stdux` | — | Store Doubleword with Update Indexed |
| `stdx` | `stdx` | — | Store Doubleword Indexed |
## Syntax
```asm
std [RS], [ds]([RA0])
stdu [RS], [ds]([RA])
stdux [RS], [RA], [RB]
stdx [RS], [RA0], [RB]
```
## Encoding
### `std` — form `DS`
- **Opcode word:** `0xf8000000`
- **Primary opcode (bits 0–5):** `62`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
| 16–29 | `DS` | 14-bit signed word-scaled displacement |
| 30–31 | `XO` | extended opcode |
### `stdu` — form `DS`
- **Opcode word:** `0xf8000001`
- **Primary opcode (bits 0–5):** `62`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
| 16–29 | `DS` | 14-bit signed word-scaled displacement |
| 30–31 | `XO` | extended opcode |
### `stdux` — form `X`
- **Opcode word:** `0x7c00016a`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `181`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `stdx` — form `X`
- **Opcode word:** `0x7c00012a`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `149`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RS` | std: read; stdu: read; stdux: read; stdx: read | Source GPR (alias for RD in some stores). |
| `RA` | std: read; stdu: read; stdu: write; stdux: read; stdux: write | Source GPR (`r0`–`r31`). |
| `ds` | std: read; stdu: read | 14-bit signed word-aligned displacement (`DS << 2`). |
| `RB` | stdux: read; stdx: read | Source GPR. |
| `RA0` | stdx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
## Register Effects
### `std`
- **Reads (always):** `RS`, `RA`, `ds`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
### `stdu`
- **Reads (always):** `RS`, `RA`, `ds`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** _none_
### `stdux`
- **Reads (always):** `RS`, `RA`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** _none_
### `stdx`
- **Reads (always):** `RS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- (RA|0) + EXTS(ds || 0b00)
MEM(EA, 8) <- (RS)
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`std`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="std"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:575`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L575)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:69`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L69)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:399`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L399)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1399-1407`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1399-L1407)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::std => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(instr.ds() as i64 as u64) as u32;
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
if t.has_active_reservers() { t.invalidate_for_write(ea); }
}
mem.write_u64(ea, ctx.gpr[instr.rs()]);
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::stdu => {
let ea = ctx.gpr[instr.ra()].wrapping_add(instr.ds() as i64 as u64) as u32;
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
if t.has_active_reservers() { t.invalidate_for_write(ea); }
}
mem.write_u64(ea, ctx.gpr[instr.rs()]);
ctx.gpr[instr.ra()] = ea as u64;
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::stdux => {
let ea = ctx.gpr[instr.ra()].wrapping_add(ctx.gpr[instr.rb()]) as u32;
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
if t.has_active_reservers() { t.invalidate_for_write(ea); }
}
mem.write_u64(ea, ctx.gpr[instr.rs()]);
ctx.gpr[instr.ra()] = ea as u64;
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::stdx => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]) as u32;
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
if t.has_active_reservers() { t.invalidate_for_write(ea); }
}
mem.write_u64(ea, ctx.gpr[instr.rs()]);
ctx.pc += 4;
}
```