# `stvx` — Store Vector Indexed
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0001ce`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stvx` | `stvx` | — | Store Vector Indexed |
| `stvx128` | `stvx128` | — | Store Vector Indexed 128 |
## Syntax
```asm
stvx [VS], [RA0], [RB]
stvx128 [VS], [RA0], [RB]
```
## Encoding
### `stvx` — form `X`
- **Opcode word:** `0x7c0001ce`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `231`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `stvx128` — form `VX128_1`
- **Opcode word:** `0x100001c3`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `451`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VS` | stvx: read; stvx128: read | Source vector register (alias for VD on stores). |
| `RA0` | stvx: read; stvx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | stvx: read; stvx128: read | Source GPR. |
## Register Effects
### `stvx`
- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
### `stvx128`
- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- ((RA|0) + (RB)) & ~0xF ; align to 16
MEM(EA, 16) <- byteswap(VS)
```
## C Translation Example
```c
/* stvx VS, RA, RB — 16-byte aligned store of a vector register */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
uint32_t ea = (uint32_t)((base + r[insn.RB]) & ~(uint64_t)0xF);
mem_write_vec128_be(ea, v[insn.VS]);
```
## Implementation References
**`stvx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:193`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L193)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:79`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L79)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:791`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L791)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1849-1859`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1849-L1859)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::stvx => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
// PPCBUG-511: stvx was missing invalidate_for_write.
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
if t.has_active_reservers() { t.invalidate_for_write(ea); }
}
let bytes = ctx.vr[instr.rs()].as_bytes();
for i in 0..16 { mem.write_u8(ea + i as u32, bytes[i]); }
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::stvx128 => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = (ea.wrapping_add(ctx.gpr[instr.rb()]) & !0xF) as u32;
// PPCBUG-511: stvx128 was missing invalidate_for_write.
if let Some(t) = ctx.reservation_table.as_ref().filter(|t| t.is_enabled()) {
if t.has_active_reservers() { t.invalidate_for_write(ea); }
}
let bytes = ctx.vr[instr.vs128()].as_bytes();
for i in 0..16 { mem.write_u8(ea + i as u32, bytes[i]); }
ctx.pc += 4;
}
```