# `lvsr` — Load Vector for Shift Right Indexed
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00004c`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `lvsr` | `lvsr` | — | Load Vector for Shift Right Indexed |
| `lvsr128` | `lvsr128` | — | Load Vector for Shift Right Indexed 128 |
## Syntax
```asm
lvsr [VD], [RA0], [RB]
lvsr128 [VD], [RA0], [RB]
```
## Encoding
### `lvsr` — form `X`
- **Opcode word:** `0x7c00004c`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `38`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `lvsr128` — form `VX128_1`
- **Opcode word:** `0x10000043`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `67`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RA0` | lvsr: read; lvsr128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | lvsr: read; lvsr128: read | Source GPR. |
| `VD` | lvsr: write; lvsr128: write | Destination vector register. |
## Register Effects
### `lvsr`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `lvsr128`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
addr_lo <- ((RA|0) + (RB))[60:63]
for i in 0..15: VD[i] <- 16 − addr_lo + i
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`lvsr`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvsr"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:126`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L126)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:46`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L46)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:762`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L762)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2530-2539`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2530-L2539)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::lvsr | PpcOpcode::lvsr128 => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]);
let sh = (ea & 0xF) as u8;
let mut r = [0u8; 16];
for i in 0..16 { r[i] = (16 - sh) + i as u8; }
let vd = if matches!(instr.opcode, PpcOpcode::lvsr128) { instr.vd128() } else { instr.rd() };
ctx.vr[vd] = xenia_types::Vec128::from_bytes(r);
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::lvsr | PpcOpcode::lvsr128 => {
let ea = if instr.ra() == 0 { 0u64 } else { ctx.gpr[instr.ra()] };
let ea = ea.wrapping_add(ctx.gpr[instr.rb()]);
let sh = (ea & 0xF) as u8;
let mut r = [0u8; 16];
for i in 0..16 { r[i] = (16 - sh) + i as u8; }
let vd = if matches!(instr.opcode, PpcOpcode::lvsr128) { instr.vd128() } else { instr.rd() };
ctx.vr[vd] = xenia_types::Vec128::from_bytes(r);
ctx.pc += 4;
}
```