# `vaddcuw` — Vector Add Carryout Unsigned Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000180`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vaddcuw` | `vaddcuw` | — | Vector Add Carryout Unsigned Word |

## Syntax

```asm
vaddcuw [VD], [VA], [VB]
```

## Encoding

### `vaddcuw` — form `VX`

- **Opcode word:** `0x10000180`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `384`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vaddcuw: read | Source A vector register. |
| `VB` | vaddcuw: read | Source B vector register. |
| `VD` | vaddcuw: write | Destination vector register. |

## Register Effects

### `vaddcuw`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vaddcuw`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vaddcuw"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:325`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L325)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:89`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L89)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:466`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L466)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3380-3390`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3380-L3390)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vaddcuw => {
            let a = ctx.vr[instr.ra()].as_u32x4();
            let b = ctx.vr[instr.rb()].as_u32x4();
            let mut r = [0u32; 4];
            for i in 0..4 {
                let (_, c) = a[i].overflowing_add(b[i]);
                r[i] = if c { 1 } else { 0 };
            }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Carry-out only — the sum is discarded.** Each of the four 32-bit lanes computes `1` if `VA[i] + VB[i]` overflows in unsigned arithmetic, else `0`. The actual modulo sum lives wherever a paired [`vadduwm`](vadduwm.md) is scheduled.
- **Big-endian word lanes.** Lane 0 (`VD[0..3]` after `stvx`) is the most-significant word. Each lane is 32-bit unsigned; output values are exactly `0` or `1`, padded to 32 bits.
- **Builds wide-integer adds.** Pair `vaddcuw` with [`vadduwm`](vadduwm.md) and a left-byte shift to chain four 32-bit adds into a single 128-bit add — the canonical Altivec implementation of `__uint128_t` arithmetic. To carry into the *next* lane you typically apply [`vsldoi`](vsldoi.md) by 4 bytes and a [`vadduwm`](vadduwm.md).
- **Unsigned only.** There is no `vaddcsw` (signed-carry) — the operation is intrinsically unsigned because "carry" is undefined for signed two's-complement.
- **No `VSCR[SAT]` update.** Modulo carry is always representable; nothing saturates. XER is also untouched (Altivec never updates `XER[CA]`).
- **No VMX128 sibling.** Only the 32-register VX form exists.
- **Aliasing legal.** `vaddcuw v3, v3, v4` works as expected.

## Related Instructions

- [`vadduwm`](vadduwm.md) — the modulo sum that `vaddcuw` complements; together they form a full 32-bit-with-carry add.
- [`vsubcuw`](vsubcuw.md) — the matching borrow-out (returns `1` when *no* borrow occurred — i.e. when `VA[i] >= VB[i]`).
- [`vsldoi`](vsldoi.md) — used to align the carry vector for the next lane during multi-precision chains.
- [`vaddubm`](vaddubm.md), [`vadduhm`](vadduhm.md) — modulo siblings at narrower lane widths (no carrying-instruction variant exists for 8- or 16-bit lanes).

## IBM Reference

- [AIX 7.3 — `vaddcuw` (Vector Add Carry-Out Unsigned Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vaddcuw-vector-add-carryout-unsigned-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — multi-precision arithmetic idiom](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)