# `vavgsw` — Vector Average Signed Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000582`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vavgsw` | `vavgsw` | — | Vector Average Signed Word |

## Syntax

```asm
vavgsw [VD], [VA], [VB]
```

## Encoding

### `vavgsw` — form `VX`

- **Opcode word:** `0x10000582`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `1410`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vavgsw: read | Source A vector register. |
| `VB` | vavgsw: read | Source B vector register. |
| `VD` | vavgsw: write | Destination vector register. |

## Register Effects

### `vavgsw`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vavgsw`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vavgsw"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:457`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L457)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:92`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L92)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:537`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L537)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3442-3449`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3442-L3449)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vavgsw => {
            let a = crate::vmx::as_i32x4(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
            let mut r = [0i32; 4];
            for i in 0..4 { r[i] = crate::vmx::avg_i32(a[i], b[i]); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Four signed-word rounding averages.** Each `VD[i] = (VA[i] + VB[i] + 1) >> 1`, computed in 64-bit arithmetic to avoid intermediate overflow, then truncated back to `int32`. Rounding is half-up toward +∞.
- **Big-endian word lanes.** Lane 0 (`VD[0..3]` after `stvx`) is the most-significant word.
- **No `VSCR[SAT]` impact.** The mathematical result always fits in `int32`. Xenia's `crate::vmx::avg_i32` widens to `i64` ([`crates/xenia-cpu/src/vmx.rs`](../../xenia-rs/crates/xenia-cpu/src/vmx.rs)).
- **No XER side effects.**
- **Aliasing legal.**
- **No VMX128 sibling.**

## Related Instructions

- [`vavguw`](vavguw.md) — same width, unsigned rounding average.
- [`vavgsb`](vavgsb.md), [`vavgsh`](vavgsh.md) — signed rounding average at byte / half width.
- [`vadduwm`](vadduwm.md), [`vaddsws`](vaddsws.md) — addition variants without the divide step.
- [`vsubuwm`](vsubuwm.md) — modulo subtract; difference computation before averaging.

## IBM Reference

- [AIX 7.3 — `vavgsw` (Vector Average Signed Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vavgsw-vector-average-signed-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Average Instructions](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)