# `vmrglb` — Vector Merge Low Byte

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000010c`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmrglb` | `vmrglb` | — | Vector Merge Low Byte |

## Syntax

```asm
vmrglb [VD], [VA], [VB]
```

## Encoding

### `vmrglb` — form `VX`

- **Opcode word:** `0x1000010c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `268`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmrglb: read | Source A vector register. |
| `VB` | vmrglb: read | Source B vector register. |
| `VD` | vmrglb: write | Destination vector register. |

## Register Effects

### `vmrglb`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmrglb`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmrglb"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:996`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L996)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:105`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L105)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:458`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L458)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3990-3997`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3990-L3997)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmrglb => {
            let a = ctx.vr[instr.ra()].as_bytes();
            let b = ctx.vr[instr.rb()].as_bytes();
            let mut r = [0u8; 16];
            for i in 0..8 { r[2*i] = a[8+i]; r[2*i+1] = b[8+i]; }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Interleave the low (least-significant) eight bytes** of two vectors: `VD = {VA[8], VB[8], VA[9], VB[9], …, VA[15], VB[15]}`. "Low" in PPC big-endian terms means the eight bytes at the higher byte addresses after `stvx`.
- **Pairs with [`vmrghb`](vmrghb.md).** Together they cover all 32 input bytes — one `vmrghb` plus one `vmrglb` is the standard 16-byte "interleave-then-store" pattern.
- **Common usage.** Second half of an AoS-from-SoA transpose for 8-bit channels (the high half is produced by `vmrghb`, the low half by `vmrglb`).
- **No `VSCR` interaction, no XER, no exceptions.** Pure permute.
- **Aliasing legal.** `vmrglb v3, v3, v3` doubles each low byte of `v3`.
- **No VMX128 sibling.**
- **Equivalent to x86 `_mm_unpacklo_epi8`** modulo lane-numbering convention.

## Related Instructions

- [`vmrghb`](vmrghb.md) — the "high half" mirror.
- [`vmrglh`](vmrglh.md), [`vmrglw`](vmrglw.md) — low-half merge at half / word width.
- [`vperm`](vperm.md), [`vsldoi`](vsldoi.md) — programmable / static permute primitives.
- [`vupklsb`](vupklsb.md) — sign-extending unpack of the low half.

## IBM Reference

- [AIX 7.3 — `vmrglb` (Vector Merge Low Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmrglb-vector-merge-low-byte-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute / Merge](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)