# `vmsumshm` — Vector Multiply-Sum Signed Half Word Modulo

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000028`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmsumshm` | `vmsumshm` | — | Vector Multiply-Sum Signed Half Word Modulo |

## Syntax

```asm
vmsumshm [VD], [VA], [VB], [VC]
```

## Encoding

### `vmsumshm` — form `VA`

- **Opcode word:** `0x10000028`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `40`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmsumshm: read | Source A vector register. |
| `VB` | vmsumshm: read | Source B vector register. |
| `VC` | vmsumshm: read | Source C vector register / 3-bit selector. |
| `VD` | vmsumshm: write | Destination vector register. |

## Register Effects

### `vmsumshm`

- **Reads (always):** `VA`, `VB`, `VC`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmsumshm`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsumshm"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1042`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1042)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:107`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L107)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:583`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L583)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3625-3638`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3625-L3638)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmsumshm => {
            let a = crate::vmx::as_i16x8(ctx.vr[instr.ra()]);
            let b = crate::vmx::as_i16x8(ctx.vr[instr.rb()]);
            let c = crate::vmx::as_i32x4(ctx.vr[instr.rc()]);
            let mut r = [0i32; 4];
            for i in 0..4 {
                let s = (a[2*i] as i32 * b[2*i] as i32)
                    .wrapping_add(a[2*i+1] as i32 * b[2*i+1] as i32)
                    .wrapping_add(c[i]);
                r[i] = s;
            }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Signed half-word multiply-sum, modulo.** Per word lane:
  ```
  VD[i] = (VC[i] + int16(VA[2*i]) * int16(VB[2*i])
                 + int16(VA[2*i+1]) * int16(VB[2*i+1])) mod 2^32
  ```
  Two signed-half × signed-half products plus a signed-word accumulator → one signed word per output lane.
- **Modulo wrap, never saturates.** **`VSCR[SAT]` is not touched** — wraparound silently. Use [`vmsumshs`](vmsumshs.md) for the saturating variant.
- **Big-endian half lanes.** Lane 0 is the most-significant half; output word `i` consumes halves `2*i` and `2*i+1`.
- **No XER, no exceptions.**
- **Aliasing legal.**
- **No VMX128 sibling.**
- **Common usage.** Q15 dot products of paired audio samples, 2-tap signed FIR coefficients.

## Related Instructions

- [`vmsumshs`](vmsumshs.md) — same shape with saturating output.
- [`vmsumuhm`](vmsumuhm.md) / [`vmsumuhs`](vmsumuhs.md) — unsigned half multiply-sum.
- [`vmsumubm`](vmsumubm.md), [`vmsummbm`](vmsummbm.md) — multiply-sum at byte width.
- [`vmhaddshs`](vmhaddshs.md), [`vmhraddshs`](vmhraddshs.md) — per-lane multiply-add (no horizontal reduction).
- [`vsum2sws`](vsum2sws.md), [`vsumsws`](vsumsws.md) — pure horizontal sums.

## IBM Reference

- [AIX 7.3 — `vmsumshm` (Vector Multiply-Sum Signed Half Word Modulo)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmsumshm-vector-multiply-sum-signed-half-word-modulo-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)