# `vmsumuhs` — Vector Multiply-Sum Unsigned Half Word Saturate

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000027`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmsumuhs` | `vmsumuhs` | — | Vector Multiply-Sum Unsigned Half Word Saturate |

## Syntax

```asm
vmsumuhs [VD], [VA], [VB], [VC]
```

## Encoding

### `vmsumuhs` — form `VA`

- **Opcode word:** `0x10000027`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `39`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmsumuhs: read | Source A vector register. |
| `VB` | vmsumuhs: read | Source B vector register. |
| `VC` | vmsumuhs: read | Source C vector register / 3-bit selector. |
| `VD` | vmsumuhs: write | Destination vector register. |
| `VSCR` | vmsumuhs: write | Vector Status and Control Register (NJ/SAT bits). |

## Register Effects

### `vmsumuhs`

- **Reads (always):** `VA`, `VB`, `VC`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_

## Status-Register Effects

- `vmsumuhs`: **VSCR[SAT]** may be stickied on saturating vector operations.

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmsumuhs`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsumuhs"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1062`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1062)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:107`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L107)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:582`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L582)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3609-3624`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3609-L3624)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmsumuhs => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let c = ctx.vr[instr.rc()].as_u32x4();
            let mut r = [0u32; 4]; let mut sat = false;
            for i in 0..4 {
                let s = (a[2*i] as u64 * b[2*i] as u64)
                    + (a[2*i+1] as u64 * b[2*i+1] as u64)
                    + c[i] as u64;
                let (v, overflow) = if s > u32::MAX as u64 { (u32::MAX, true) } else { (s as u32, false) };
                r[i] = v; sat |= overflow;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Unsigned half-word multiply-sum, saturating.** Per word lane:
  ```
  VD[i] = clamp(VC[i] + uint16(VA[2*i]) * uint16(VB[2*i])
                     + uint16(VA[2*i+1]) * uint16(VB[2*i+1]), 0, UINT32_MAX)
  ```
  Two unsigned-half × unsigned-half products plus an unsigned-word accumulator, clamped to `uint32`.
- **Wide-then-clamp ordering.** Xenia accumulates into `u64` first and clamps the *final* sum to `u32` ([`crates/xenia-cpu/src/interpreter.rs`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs)) — matches the IBM spec.
- **`VSCR[SAT]` is sticky-set** if any lane clamps. Only the upper bound `0xFFFF_FFFF` ever triggers; unsigned overflow on the low side is impossible.
- **Big-endian half lanes.** Lane 0 is the most-significant half.
- **No XER, no exceptions.**
- **Aliasing legal.**
- **No VMX128 sibling.**
- **Common usage.** Per-pixel summed-area calculations with overflow detection; high-precision unsigned-half FIR convolution.

## Related Instructions

- [`vmsumuhm`](vmsumuhm.md) — same shape, modulo (no clamp, no SAT flag).
- [`vmsumshs`](vmsumshs.md) — signed half multiply-sum, saturating.
- [`vmsumubm`](vmsumubm.md), [`vmsummbm`](vmsummbm.md) — multiply-sum at byte width.
- [`vadduws`](vadduws.md) — unsigned saturating word add for further accumulation.
- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear `VSCR[SAT]`.

## IBM Reference

- [AIX 7.3 — `vmsumuhs` (Vector Multiply-Sum Unsigned Half Word Saturate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmsumuhs-vector-multiply-sum-unsigned-half-word-saturate-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)