# `vmuleub` — Vector Multiply Even Unsigned Byte

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000208`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmuleub` | `vmuleub` | — | Vector Multiply Even Unsigned Byte |

## Syntax

```asm
vmuleub [VD], [VA], [VB]
```

## Encoding

### `vmuleub` — form `VX`

- **Opcode word:** `0x10000208`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `520`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmuleub: read | Source A vector register. |
| `VB` | vmuleub: read | Source B vector register. |
| `VD` | vmuleub: write | Destination vector register. |

## Register Effects

### `vmuleub`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmuleub`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmuleub"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1096`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1096)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:108`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L108)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:478`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L478)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3453-3460`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3453-L3460)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vmuleub => {
            let a = ctx.vr[instr.ra()].as_bytes();
            let b = ctx.vr[instr.rb()].as_bytes();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = a[2 * i] as u16 * b[2 * i] as u16; }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Even-lane multiply.** Only the *even-indexed* bytes of `VA` and `VB` participate — lanes 0, 2, 4, 6, 8, 10, 12, 14 (big-endian indexing, MSB-first). Each unsigned-byte × unsigned-byte product widens to an unsigned 16-bit half-word and is written to the corresponding half-word of `VD`. The odd lanes are ignored.
- **Lane-count reduction.** Input has 16 byte lanes; output has 8 half-word lanes. The pairing is `VD.h[i] = VA.b[2*i] * VB.b[2*i]` for `i ∈ 0..7`.
- **No overflow possible.** 8-bit × 8-bit unsigned ≤ `0xFF * 0xFF = 0xFE01`, which fits in 16 bits. `VSCR[SAT]` is **not** touched; this is a modulo-equivalent op even though no modulo is needed.
- **Pair with [`vmuloub`](vmuloub.md) to get all 16 products.** Software that wants every byte × byte product typically issues `vmuleub` + `vmuloub` and then interleaves the two half-word vectors (`vmrghh`/`vmrglh`) or sums them (`vmsumubm`).
- **No `Rc`, no XER, no FPSCR.** VMX multiply never touches CR, CA, OV, or VSCR.
- **No VMX128 sibling.** Xbox 360 code that needs this pattern typically goes through [`vmsumubm`](vmsumubm.md) instead.

## Related Instructions

- [`vmuloub`](vmuloub.md) — odd-lane twin (bytes 1, 3, …, 15).
- [`vmulesb`](vmulesb.md), [`vmulosb`](vmulosb.md) — signed-byte even/odd multiplies.
- [`vmuleuh`](vmuleuh.md), [`vmulouh`](vmulouh.md) — unsigned-half-word even/odd multiplies (→ word lanes).
- [`vmulesh`](vmulesh.md), [`vmulosh`](vmulosh.md) — signed-half-word even/odd.
- [`vmsumubm`](vmsumubm.md) — fused multiply-sum unsigned-byte-modulo; often replaces the even/odd pair when the caller only needs the sum.
- [`vmrghh`](vmrghh.md), [`vmrglh`](vmrglh.md) — interleave the even/odd half-word results.

## IBM Reference

- [AIX 7.3 — `vmuleub` (Vector Multiply Even Unsigned Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmuleub-vector-multiply-even-unsigned-byte-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)