# `vrlh` — Vector Rotate Left Integer Half Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000044`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vrlh` | `vrlh` | — | Vector Rotate Left Integer Half Word |

## Syntax

```asm
vrlh [VD], [VA], [VB]
```

## Encoding

### `vrlh` — form `VX`

- **Opcode word:** `0x10000044`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `68`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vrlh: read | Source A vector register. |
| `VB` | vrlh: read | Source B vector register. |
| `VD` | vrlh: write | Destination vector register. |

## Register Effects

### `vrlh`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vrlh`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vrlh"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1294`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1294)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:119`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L119)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:443`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L443)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3908-3915`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3908-L3915)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vrlh => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = a[i].rotate_left((b[i] & 0xF) as u32); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Per-lane left-rotate of half-words.** For each of the 8 half-word lanes, `VD.h[i] = rotate_left(VA.h[i], VB.h[i] & 0xF)`. Low 4 bits of each shift-count half-word are used.
- **Per-lane shift counts.** Splat first (`vsplth`) if a uniform rotate is needed.
- **Big-endian half-word lanes.** Lane 0 is the most significant pair of bytes.
- **No overflow, no saturation.** Rotation is information-preserving.
- **No `Rc`, no XER, no VSCR effect.**
- **No VMX128 sibling.**

## Related Instructions

- [`vrlb`](vrlb.md), [`vrlw`](vrlw.md) — byte / word rotate siblings.
- [`vslh`](vslh.md), [`vsrh`](vsrh.md), [`vsrah`](vsrah.md) — half-word shift-left / logical-right / arithmetic-right.
- [`vsl`](vsl.md), [`vsr`](vsr.md) — bit-level whole-register shifts.
- [`vsplth`](vsplth.md) — splat to build a uniform shift-count vector.

## IBM Reference

- [AIX 7.3 — `vrlh` (Vector Rotate Left Integer Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vrlh-vector-rotate-left-integer-half-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)