# `vspltisb` — Vector Splat Immediate Signed Byte

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000030c`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vspltisb` | `vspltisb` | — | Vector Splat Immediate Signed Byte |

## Syntax

```asm
vspltisb [VD], [SIMM]
```

## Encoding

### `vspltisb` — form `VX`

- **Opcode word:** `0x1000030c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `780`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `SIMM` | vspltisb: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
| `VD` | vspltisb: write | Destination vector register. |

## Register Effects

### `vspltisb`

- **Reads (always):** `SIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vspltisb`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vspltisb"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1536`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1536)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:123`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L123)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:503`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L503)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2364-2369`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2364-L2369)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vspltisb => {
            let simm = ((instr.raw >> 16) & 0x1F) as i8;
            let simm = if simm & 0x10 != 0 { simm | !0x1F } else { simm };
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_bytes([simm as u8; 16]);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Splat a 5-bit signed immediate across all 16 byte lanes.** The `SIMM` field (bits 11–15) is sign-extended from 5 bits to 8 — so the representable range is `[−16, +15]`. Values `0x10..0x1F` decode as negative (`−16..−1`).
- **Constant-generation primitive.** `vspltisb vD, 0` is the canonical "all-bytes-zero" vector (same net effect as `vxor vD, vD, vD`). `vspltisb vD, -1` is the all-ones mask. `vspltisb vD, 1` broadcasts `{1, 1, …, 1}` for vector-increment tricks.
- **No source register.** The op doesn't read `VA` / `VB`; this saves a register-file read port and keeps constant-generation cheap.
- **Big-endian lane order** (all lanes identical anyway).
- **No flags, no VSCR.**
- **No VMX128 sibling.** Xenon uses the same encoding.

## Related Instructions

- [`vspltish`](vspltish.md), [`vspltisw`](vspltisw.md) — half-word and word immediate splats (still sign-extended from 5 bits).
- [`vspltb`](vspltb.md), [`vsplth`](vsplth.md), [`vspltw`](vspltw.md) — register-indexed splats.
- [`vxor`](vxor.md) — alternative "zero vector" idiom when `vD` is already known.

## IBM Reference

- [AIX 7.3 — `vspltisb` (Vector Splat Immediate Signed Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vspltisb-vector-splat-immediate-signed-byte-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)