# `vspltisw` — Vector Splat Immediate Signed Word
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000038c`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vspltisw` | `vspltisw` | — | Vector Splat Immediate Signed Word |
| `vspltisw128` | `vspltisw128` | — | Vector128 Splat Immediate Signed Word |
## Syntax
```asm
vspltisw [VD], [SIMM]
vspltisw128 [VD], [SIMM]
```
## Encoding
### `vspltisw` — form `VX`
- **Opcode word:** `0x1000038c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `908`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |
### `vspltisw128` — form `VX128_3`
- **Opcode word:** `0x18000770`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `1904`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `SIMM` | vspltisw: read; vspltisw128: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
| `VD` | vspltisw: write; vspltisw128: write | Destination vector register. |
## Register Effects
### `vspltisw`
- **Reads (always):** `SIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `vspltisw128`
- **Reads (always):** `SIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vspltisw`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vspltisw"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1580`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1580)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:123`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L123)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:516`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L516)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2356-2363`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2356-L2363)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::vspltisw | PpcOpcode::vspltisw128 => {
let simm = ((instr.raw >> 16) & 0x1F) as i32;
let simm = if simm & 0x10 != 0 { simm | !0x1F } else { simm }; // sign extend 5-bit
let val = simm as u32;
let vd = if matches!(instr.opcode, PpcOpcode::vspltisw128) { instr.vd128() } else { instr.rd() };
ctx.vr[vd] = xenia_types::Vec128::from_u32x4(val, val, val, val);
ctx.pc += 4;
}
```
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::vspltisw | PpcOpcode::vspltisw128 => {
let simm = ((instr.raw >> 16) & 0x1F) as i32;
let simm = if simm & 0x10 != 0 { simm | !0x1F } else { simm }; // sign extend 5-bit
let val = simm as u32;
let vd = if matches!(instr.opcode, PpcOpcode::vspltisw128) { instr.vd128() } else { instr.rd() };
ctx.vr[vd] = xenia_types::Vec128::from_u32x4(val, val, val, val);
ctx.pc += 4;
}
```