# `vsrh` — Vector Shift Right Half Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000244`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vsrh` | `vsrh` | — | Vector Shift Right Half Word |

## Syntax

```asm
vsrh [VD], [VA], [VB]
```

## Encoding

### `vsrh` — form `VX`

- **Opcode word:** `0x10000244`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `580`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vsrh: read | Source A vector register. |
| `VB` | vsrh: read | Source B vector register. |
| `VD` | vsrh: write | Destination vector register. |

## Register Effects

### `vsrh`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vsrh`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsrh"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1633`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1633)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:124`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L124)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:484`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L484)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3892-3899`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3892-L3899)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vsrh => {
            let a = ctx.vr[instr.ra()].as_u16x8();
            let b = ctx.vr[instr.rb()].as_u16x8();
            let mut r = [0u16; 8];
            for i in 0..8 { r[i] = a[i] >> (b[i] & 0xF); }
            ctx.vr[instr.rd()] = xenia_types::Vec128::from_u16x8_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Per-lane logical right-shift of half-words.** `VD.h[i] = VA.h[i] >> (VB.h[i] & 0xF)` — zero-fill. Low 4 bits of each shift-count half-word honoured.
- **Per-lane shift counts.** Splat via [`vsplth`](vsplth.md) / [`vspltish`](vspltish.md) for uniform shifts.
- **Zero-fill.** Use [`vsrah`](vsrah.md) for sign-preserving right shift.
- **Big-endian half-word lanes.**
- **No flags, no VSCR.**
- **No VMX128 sibling.**

## Related Instructions

- [`vsrah`](vsrah.md) — arithmetic-right half-word.
- [`vslh`](vslh.md) — logical-left half-word.
- [`vrlh`](vrlh.md) — half-word rotate.
- [`vsrb`](vsrb.md), [`vsrw`](vsrw.md) — byte / word logical-right.

## IBM Reference

- [AIX 7.3 — `vsrh` (Vector Shift Right Integer Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsrh-vector-shift-right-integer-half-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)