# `vsum4sbs` — Vector Sum Across Partial (1/4) Signed Byte Saturate

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000708`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vsum4sbs` | `vsum4sbs` | — | Vector Sum Across Partial (1/4) Signed Byte Saturate |

## Syntax

```asm
vsum4sbs [VD], [VA], [VB]
```

## Encoding

### `vsum4sbs` — form `VX`

- **Opcode word:** `0x10000708`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `1800`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vsum4sbs: read | Source A vector register. |
| `VB` | vsum4sbs: read | Source B vector register. |
| `VD` | vsum4sbs: write | Destination vector register. |
| `VSCR` | vsum4sbs: write | Vector Status and Control Register (NJ/SAT bits). |

## Register Effects

### `vsum4sbs`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_

## Status-Register Effects

- `vsum4sbs`: **VSCR[SAT]** may be stickied on saturating vector operations.

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vsum4sbs`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsum4sbs"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1781`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1781)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:127`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L127)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:547`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L547)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3680-3692`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3680-L3692)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vsum4sbs => {
            let a = crate::vmx::as_i8x16(ctx.vr[instr.ra()]);
            let c = crate::vmx::as_i32x4(ctx.vr[instr.rb()]);
            let mut r = [0i32; 4]; let mut sat = false;
            for i in 0..4 {
                let s = a[4*i] as i64 + a[4*i+1] as i64 + a[4*i+2] as i64 + a[4*i+3] as i64 + c[i] as i64;
                let (v, o) = crate::vmx::sat_i64_to_i32(s);
                r[i] = v; sat |= o;
            }
            if sat { ctx.set_vscr_sat(true); }
            ctx.vr[instr.rd()] = crate::vmx::from_i32x4(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Per-word 4-byte partial sum (signed).** For each of the 4 output word lanes, sum 4 signed bytes of `VA` plus the matching signed word of `VB`, then saturate to `int32`. Input byte layout: `VD.w[i] = sat(VA.b[4*i] + VA.b[4*i+1] + VA.b[4*i+2] + VA.b[4*i+3] + VB.w[i])`.
- **Sticky VSCR[SAT]** set on overflow.
- **Typical use: accumulate per-channel sums** (e.g. for a colour-averaging or luminance operator).
- **Big-endian byte / word lanes.**
- **No `Rc`, no XER.**
- **No VMX128 sibling.**

## Related Instructions

- [`vsum4shs`](vsum4shs.md) — signed half-word variant.
- [`vsum4ubs`](vsum4ubs.md) — unsigned byte variant.
- [`vsumsws`](vsumsws.md), [`vsum2sws`](vsum2sws.md) — reductions that accumulate fewer output lanes.
- [`vmsummbm`](vmsummbm.md) — fused signed-byte multiply-sum (different shape, same "horizontal reduce" flavour).

## IBM Reference

- [AIX 7.3 — `vsum4sbs` (Vector Sum across Partial (1/4) Saturated Signed Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsum4sbs-vector-sum-across-partial-14-saturated-signed-byte-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)