# `vpermwi128` — Vector128 Permutate Word Immediate

> **Category:** [VMX128](../categories/vmx128.md) · **Form:** [VX128_P](../forms/VX128_P.md) · **Opcode:** `0x18000210`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vpermwi128` | `vpermwi128` | — | Vector128 Permutate Word Immediate |

## Syntax

```asm
vpermwi128 [VD], [VB], [UIMM]
```

## Encoding

### `vpermwi128` — form `VX128_P`

- **Opcode word:** `0x18000210`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `528`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `PERMl` | permute selector low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–22 | `—` | reserved |
| 23–25 | `PERMh` | permute selector high 3 bits |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VB` | vpermwi128: read | Source B vector register. |
| `UIMM` | vpermwi128: read | 16-bit unsigned immediate. Zero-extended. |
| `VD` | vpermwi128: write | Destination vector register. |

## Register Effects

### `vpermwi128`

- **Reads (always):** `VB`, `UIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
;   - Read source operands from the fields listed under Operands.
;   - Apply the arithmetic / logical / memory action described
;     in the Description field above.
;   - Write results to the destination register(s); update any
;     status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vpermwi128`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpermwi128"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1207`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1207)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:112`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L112)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:642`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L642)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4537-4548`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4537-L4548)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::vpermwi128 => {
            let imm = instr.vx128_p_perm();
            let b = ctx.vr[instr.vb128()].as_u32x4();
            let mut r = [0u32; 4];
            // Output lane i ← b[(imm >> (2 * (3-i))) & 3]
            for i in 0..4 {
                let sel = ((imm >> (2 * (3 - i))) & 3) as usize;
                r[i] = b[sel];
            }
            ctx.vr[instr.vd128()] = xenia_types::Vec128::from_u32x4_array(r);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **Word-level 4-way permute via an 8-bit immediate.** The 8-bit `PERM` immediate (carried in fields `PERMh ‖ PERMl` of the encoding) is treated as **four 2-bit selectors**, one per output word lane. Each 2-bit field selects which of `VB`'s 4 word lanes is copied to the corresponding output lane.
- **Bit layout of the immediate.** Output lane 0 (big-endian MSB word) is selected by bits 6–7 of `PERM`; lane 1 by bits 4–5; lane 2 by bits 2–3; lane 3 by bits 0–1. (In xenia: `sel = (imm >> (2 * (3-i))) & 3`.)
- **Super-set of [`vspltw`](../vmx/vspltw.md).** A splat is `vpermwi128 vD, vB, 0x00` (all lanes = word 0), `0x55` (all = word 1), `0xAA` (all = word 2), `0xFF` (all = word 3). Arbitrary shuffles like "xyzw → wzyx" are a single-instruction operation.
- **Immediate-only.** No dynamic selector vector; contrast with [`vperm`](../vmx/vperm.md).
- **Single-source.** Unlike `vperm`/`vperm128`, `vpermwi128` only reshuffles one register (`VB`); it cannot interleave two operands.
- **VMX128 register-fusion** on `VD` and `VB` (7-bit IDs).
- **No IBM AIX entry** — Xenon-only.
- **No `Rc`, no XER, no VSCR.**

## Related Instructions

- [`vperm`](../vmx/vperm.md), [`vperm128`](../vmx/vperm.md) — general byte-granularity permute (two-source).
- [`vspltw`](../vmx/vspltw.md), [`vspltw128`](../vmx/vspltw.md) — single-word splat (special case of `vpermwi128`).
- [`vsldoi`](../vmx/vsldoi.md) — static-immediate byte rotate of two registers.
- [`vrlimi128`](vrlimi128.md) — rotate + mask-insert (per-word rotate with an insert mask).

## IBM Reference

- No IBM AIX entry — this instruction is exclusive to the Xbox 360's VMX128 extension.
- Xbox 360 XDK, Altivec-128 (VMX128) extensions. Functionally equivalent to HLSL's `.xyzw`-suffix swizzle on `float4`.
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf) for the base permute semantics.