# `subfzex` — Subtract From Zero Extended > **Category:** [Integer ALU](../categories/alu.md) · **Form:** [XO](../forms/XO.md) · **Opcode:** `0x7c000190` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `subfze` | `subfzex` | — | Subtract From Zero Extended | | `subfzeo` | `subfzex` | OE=1 | Subtract From Zero Extended | | `subfze.` | `subfzex` | Rc=1 | Subtract From Zero Extended | | `subfzeo.` | `subfzex` | OE=1, Rc=1 | Subtract From Zero Extended | ## Syntax ```asm subfze[OE][Rc] [RD], [RA] ``` ## Encoding ### `subfzex` — form `XO` - **Opcode word:** `0x7c000190` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `200` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode (31) | | 6–10 | `RT` | destination GPR | | 11–15 | `RA` | source A | | 16–20 | `RB` | source B | | 21 | `OE` | overflow-enable flag | | 22–30 | `XO` | extended opcode (9 bits) | | 31 | `Rc` | record-form flag | ## Operands | Field | Role | Description | | --- | --- | --- | | `RA` | subfzex: read | Source GPR (`r0`–`r31`). | | `CA` | subfzex: read; subfzex: write | XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions. | | `RD` | subfzex: write | Destination GPR. | | `CR` | subfzex: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. | | `OE` | subfzex: write (conditional) | Overflow-enable bit. When 1, the instruction updates `XER[OV]` and stickies `XER[SO]` on signed overflow. | ## Register Effects ### `subfzex` - **Reads (always):** `RA`, `CA` - **Reads (conditional):** _none_ - **Writes (always):** `RD`, `CA` - **Writes (conditional):** `CR`, `OE` ## Status-Register Effects - `subfzex`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **XER[OV]** ← signed-overflow(result); **XER[SO]** stickies, when `OE=1`.; **XER[CA]** ← carry-out of the add / borrow-in of the subtract (always). ## Operation (pseudocode) ``` ; Pseudocode derives directly from the xenia-rs interpreter ; arm (see Implementation References). Operation semantics: ; - Read source operands from the fields listed under Operands. ; - Apply the arithmetic / logical / memory action described ; in the Description field above. ; - Write results to the destination register(s); update any ; status bits enumerated under Status-Register Effects. ; Consult the IBM AIX reference link under IBM Reference for ; canonical PPC-style pseudocode where xenia's expression is ; terse. ``` ## C Translation Example ```c /* C translation: the xenia-rs interpreter arm below in */ /* Implementation References is the authoritative semantic */ /* snapshot. Translate it line-by-line: */ /* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */ /* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */ /* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */ /* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`subfzex`** - xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="subfzex"`](../../xenia-canary/tools/ppc-instructions.xml) - xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:504`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L504) - xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:83`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L83) - xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:869`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L869) - xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:307-324`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L307-L324)
xenia-rs interpreter body (frozen snapshot) ```rust PpcOpcode::subfzex => { // PPCBUG-018: same active-poisoning shape as subfex; operate in u32. let ra32 = ctx.gpr[instr.ra()] as u32; let ca = ctx.xer_ca as u32; let result32 = (!ra32).wrapping_add(ca); // RT <- !RA + CA (no -1 term). 32-bit carry-out only when // !ra32 = u32::MAX (i.e. ra32 = 0) AND ca = 1. ctx.xer_ca = if ra32 == 0 && ca != 0 { 1 } else { 0 }; ctx.gpr[instr.rd()] = result32 as u64; if instr.oe() { let true_sum = -(ra32 as i32 as i128) - 1 + (ca as i128); overflow::apply(ctx, true_sum != (result32 as i32) as i128); } if instr.rc_bit() { ctx.update_cr_signed(0, result32 as i32 as i64); } ctx.pc += 4; } ```
## Special Cases & Edge Conditions - **`RT ← ~RA + 0 + XER[CA]` ≡ `~RA + CA`.** The subtract-side high-word terminator for a multi-word subtract chain. Implements `0 - (...) - borrow` for the high word. - **`RB` field unused.** - **Carry-out predicate.** `CA' = (~RA != 0) || (CA != 0)` ([`interpreter.rs:180`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L180)). Only `RA == ~0 && CA == 0` produces `CA' = 0`; every other case gives no-borrow. - **`OE=1`** should set `XER[OV]` on signed overflow; xenia-rs ignores. - **64-bit CR update on Xenon, 32-bit in xenia-rs.** [`interpreter.rs:183`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L183). - **`XER[CA]` must be initialised** by an earlier carrying instruction. - **Common idiom: extracting `XER[CA]` as 0/-1.** `subfze rT, rN` (where `rN == 0`) materialises `XER[CA]` to `0` or `-1` (`-1 = ~0 + CA = -1 + CA`); pair with [`addzex`](addzex.md) for `0/1` instead. ## Related Instructions - [`subfmex`](subfmex.md) — terminator with `~RA + (−1) + CA`. - [`subfex`](subfex.md), [`subfcx`](subfcx.md) — chain middle / seed. - [`addzex`](addzex.md) — dual; produces 0/1 from `CA`. - [`negx`](negx.md) — `subfze` with `RA = 0` and `CA = 1` is functionally similar. ## IBM Reference - [AIX 7.3 — `subfze` (Subtract From Zero Extended)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-subfze-subtract-from-zero-extended-instruction)