# `xori` — XOR Immediate

> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x68000000`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `xori` | `xori` | — | XOR Immediate |

## Syntax

```asm
xori [RA], [RS], [UIMM]
```

## Encoding

### `xori` — form `D`

- **Opcode word:** `0x68000000`
- **Primary opcode (bits 0–5):** `26`
- **Extended opcode:** —
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RS` | xori: read | Source GPR (alias for RD in some stores). |
| `UIMM` | xori: read | 16-bit unsigned immediate. Zero-extended. |
| `RA` | xori: write | Source GPR (`r0`–`r31`). |

## Register Effects

### `xori`

- **Reads (always):** `RS`, `UIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
RA <- (RS) ^ (0x0000 || UIMM)
```

## C Translation Example

```c
/* C translation: the xenia-rs interpreter arm below in           */
/* Implementation References is the authoritative semantic        */
/* snapshot. Translate it line-by-line:                            */
/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`xori`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="xori"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:839`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L839)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:132`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L132)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:349`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L349)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:520-523`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L520-L523)
<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>

```rust
        PpcOpcode::xori => {
            ctx.gpr[instr.ra()] = ctx.gpr[instr.rs()] ^ (instr.uimm16() as u64);
            ctx.pc += 4;
        }
```
</details>

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## Special Cases & Edge Conditions

- **No record form.** Like [`ori`](ori.md), there is no `xori.`. To get a CR0 update follow with `cmpwi` or use [`xorx`](xorx.md) with `Rc=1`.
- **Immediate is zero-extended** to 64 bits. Only the low 16 bits of `RA` can be flipped; the high 48 bits are passed through from `RS` unchanged.
- **`xori 0, 0, 0` is a valid NOP encoding** but the canonical NOP is `ori 0, 0, 0`. Disassemblers should still display this as `xori r0, r0, 0` or recognise it as a no-op.
- **64-bit operation in xenia-rs.** [`interpreter.rs:338`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L338) — full `u64` XOR with the immediate.
- **No `XER`, no `CR`** side effects.
- **`RA = 0` reads `r0`** (not literal zero); see [`ori`](ori.md).
- **Useful for masked toggle.** `xori rA, rS, mask` flips the bits of `rS` indicated by `mask` (low 16 bits only).

## Related Instructions

- [`xoris`](xoris.md) — companion (immediate shifted left 16).
- [`xorx`](xorx.md) — register-register XOR.
- [`eqvx`](eqvx.md) — `~(RS ^ RB)`.
- [`ori`](ori.md), [`andix`](andix.md) — sister immediate logicals.

## IBM Reference

- [AIX 7.3 — `xori` (XOR Immediate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-xori-immediate-instruction)