# `mtfsfx` — Move to FPSCR Fields
> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [XFL](../forms/XFL.md) · **Opcode:** `0xfc00058e`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `mtfsf` | `mtfsfx` | — | Move to FPSCR Fields |
| `mtfsf.` | `mtfsfx` | Rc=1 | Move to FPSCR Fields |
## Syntax
```asm
mtfsf[Rc] [FM], [FB]
```
## Encoding
### `mtfsfx` — form `XFL`
- **Opcode word:** `0xfc00058e`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `711`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (63) |
| 6 | `L` | field-select behaviour |
| 7–14 | `FM` | FPSCR field mask |
| 15 | `W` | immediate-value flag |
| 16–20 | `FRB` | source FPR |
| 21–30 | `XO` | extended opcode |
| 31 | `Rc` | record-form flag (updates CR1) |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `FM` | mtfsfx: read | 8-bit FPSCR field-mask used by `mtfsf`. |
| `FB` | mtfsfx: read | Source B floating-point register. |
| `FPSCR` | mtfsfx: write | Floating-Point Status and Control Register. |
| `CR` | mtfsfx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
## Register Effects
### `mtfsfx`
- **Reads (always):** `FM`, `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FPSCR`
- **Writes (conditional):** `CR`
## Status-Register Effects
- `mtfsfx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
## Operation (pseudocode)
```
; Pseudocode derives directly from the xenia-rs interpreter
; arm (see Implementation References). Operation semantics:
; - Read source operands from the fields listed under Operands.
; - Apply the arithmetic / logical / memory action described
; in the Description field above.
; - Write results to the destination register(s); update any
; status bits enumerated under Status-Register Effects.
; Consult the IBM AIX reference link under IBM Reference for
; canonical PPC-style pseudocode where xenia's expression is
; terse.
```
## C Translation Example
```c
/* C translation: the xenia-rs interpreter arm below in */
/* Implementation References is the authoritative semantic */
/* snapshot. Translate it line-by-line: */
/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`mtfsfx`**
- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mtfsfx"`](../../xenia-canary/tools/ppc-instructions.xml)
- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:416`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L416)
- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:55`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L55)
- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:911`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L911)
- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:3041-3054`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L3041-L3054)
xenia-rs interpreter body (frozen snapshot)
```rust
PpcOpcode::mtfsfx => {
// Move to FPSCR fields: fm mask in bits 7-14, frB value
let fm = (instr.raw >> 17) & 0xFF;
let val = ctx.fpr[instr.rb()].to_bits() as u32;
let mut mask = 0u32;
for i in 0..8 {
if fm & (1 << (7 - i)) != 0 {
mask |= 0xF << (28 - i * 4);
}
}
ctx.fpscr = (ctx.fpscr & !mask) | (val & mask);
if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
ctx.pc += 4;
}
```