# Form `VA` — VA — Vector Arithmetic (4-operand, madd-style)

## Bit Layout

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |

## Instructions Using This Form

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| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`vmhaddshs`](../vmx/vmhaddshs.md) | `0x10000020` | vmx | Vector Multiply-High and Add Signed Signed Half Word Saturate |
| [`vmhraddshs`](../vmx/vmhraddshs.md) | `0x10000021` | vmx | Vector Multiply-High Round and Add Signed Signed Half Word Saturate |
| [`vmladduhm`](../vmx/vmladduhm.md) | `0x10000022` | vmx | Vector Multiply-Low and Add Unsigned Half Word Modulo |
| [`vmsumubm`](../vmx/vmsumubm.md) | `0x10000024` | vmx | Vector Multiply-Sum Unsigned Byte Modulo |
| [`vmsummbm`](../vmx/vmsummbm.md) | `0x10000025` | vmx | Vector Multiply-Sum Mixed-Sign Byte Modulo |
| [`vmsumuhm`](../vmx/vmsumuhm.md) | `0x10000026` | vmx | Vector Multiply-Sum Unsigned Half Word Modulo |
| [`vmsumuhs`](../vmx/vmsumuhs.md) | `0x10000027` | vmx | Vector Multiply-Sum Unsigned Half Word Saturate |
| [`vmsumshm`](../vmx/vmsumshm.md) | `0x10000028` | vmx | Vector Multiply-Sum Signed Half Word Modulo |
| [`vmsumshs`](../vmx/vmsumshs.md) | `0x10000029` | vmx | Vector Multiply-Sum Signed Half Word Saturate |
| [`vsel`](../vmx/vsel.md) | `0x1000002a` | vmx | Vector Conditional Select |
| [`vperm`](../vmx/vperm.md) | `0x1000002b` | vmx | Vector Permute |
| [`vsldoi`](../vmx/vsldoi.md) | `0x1000002c` | vmx | Vector Shift Left Double by Octet Immediate |
| [`vmaddfp`](../vmx/vmaddfp.md) | `0x1000002e` | vmx | Vector Multiply-Add Floating Point |
| [`vnmsubfp`](../vmx/vnmsubfp.md) | `0x1000002f` | vmx | Vector Negative Multiply-Subtract Floating Point |

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