# Form `VX128_1` — VX128_1 — VMX128 vector load/store

## Bit Layout

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |

## Instructions Using This Form

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| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`lvsl128`](../vmx128/lvsl.md) | `0x10000003` | vmx | Load Vector for Shift Left Indexed 128 |
| [`lvsr128`](../vmx128/lvsr.md) | `0x10000043` | vmx | Load Vector for Shift Right Indexed 128 |
| [`lvewx128`](../memory/lvewx.md) | `0x10000083` | memory | Load Vector Element Word Indexed 128 |
| [`lvx128`](../memory/lvx.md) | `0x100000c3` | memory | Load Vector Indexed 128 |
| [`stvewx128`](../memory/stvewx.md) | `0x10000183` | memory | Store Vector Element Word Indexed 128 |
| [`stvx128`](../memory/stvx.md) | `0x100001c3` | memory | Store Vector Indexed 128 |
| [`lvxl128`](../memory/lvxl.md) | `0x100002c3` | memory | Load Vector Indexed LRU 128 |
| [`stvxl128`](../memory/stvxl.md) | `0x100003c3` | memory | Store Vector Indexed LRU 128 |
| [`lvlx128`](../memory/lvlx.md) | `0x10000403` | memory | Load Vector Left Indexed 128 |
| [`lvrx128`](../memory/lvrx.md) | `0x10000443` | memory | Load Vector Right Indexed 128 |
| [`stvlx128`](../memory/stvlx.md) | `0x10000503` | memory | Store Vector Left Indexed 128 |
| [`stvrx128`](../memory/stvrx.md) | `0x10000543` | memory | Store Vector Right Indexed 128 |
| [`lvlxl128`](../memory/lvlxl.md) | `0x10000603` | memory | Load Vector Left Indexed LRU 128 |
| [`lvrxl128`](../memory/lvrxl.md) | `0x10000643` | memory | Load Vector Right Indexed LRU 128 |
| [`stvlxl128`](../memory/stvlxl.md) | `0x10000703` | memory | Store Vector Left Indexed LRU 128 |
| [`stvrxl128`](../memory/stvrxl.md) | `0x10000743` | memory | Store Vector Right Indexed LRU 128 |

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