# Form `XL` — XL — Extended, Link (branch-to-LR/CTR, CR logical)

## Bit Layout

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (19) |
| 6–10 | `BT/BO` | target / branch options |
| 11–15 | `BA/BI` | source A / CR bit to test |
| 16–20 | `BB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `LK` | link flag |

## Instructions Using This Form

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| Mnemonic | Opcode | Group | Description |
| --- | --- | --- | --- |
| [`mcrf`](../control/mcrf.md) | `0x4c000000` | control | Move Condition Register Field |
| [`bclrx`](../branch/bclrx.md) | `0x4c000020` | branch | Branch Conditional to Link Register |
| [`crnor`](../control/crnor.md) | `0x4c000042` | control | Condition Register NOR |
| [`crandc`](../control/crandc.md) | `0x4c000102` | control | Condition Register AND with Complement |
| [`isync`](../alu/isync.md) | `0x4c00012c` | integer | Instruction Synchronize |
| [`crxor`](../control/crxor.md) | `0x4c000182` | control | Condition Register XOR |
| [`crnand`](../control/crnand.md) | `0x4c0001c2` | control | Condition Register NAND |
| [`crand`](../control/crand.md) | `0x4c000202` | control | Condition Register AND |
| [`creqv`](../control/creqv.md) | `0x4c000242` | control | Condition Register Equivalent |
| [`crorc`](../control/crorc.md) | `0x4c000342` | control | Condition Register OR with Complement |
| [`cror`](../control/cror.md) | `0x4c000382` | control | Condition Register OR |
| [`bcctrx`](../branch/bcctrx.md) | `0x4c000420` | branch | Branch Conditional to Count Register |

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